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path: root/src/priv-csrs.tex
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2021-09-08Merge pull request #727 from riscv/mseccfgAndrew Waterman1-0/+16
2021-09-01Clarify widths of privileged CSRs (#728)John Hauser1-1/+1
2021-08-29Add *envcfg CSR allocationsAndrew Waterman1-0/+11
2021-08-29Add mseccfg CSRAndrew Waterman1-0/+5
2021-08-28Add mconfigptr CSR (#697)Andrew Waterman1-0/+1
2021-07-22Standard CSRs don't have read side effects (#687)Andrew Waterman1-0/+3
2021-07-21Improve labels of CSR categories (#684)John Hauser1-11/+11
2021-07-13Remove or downgrade more references to N extension (#674)John Hauser1-18/+2
2020-08-28Add scontext, hcontext, and mcontext CSRs for Debug (#559)Ernie Edgar1-0/+9
2020-08-14Change "reserved for custom" to "designated for custom" (#566)John Hauser1-1/+1
2020-07-20Make it explicit that the priv arch requires ZicsrAndrew Waterman1-3/+9
2020-05-22Extend PMP scheme to support 64 regionsAndrew Waterman1-1/+4
2020-03-03Refined definition of WARL.Krste Asanovic1-1/+1
2020-02-10Update chapters 2 and 7 for Hypervisor v0.6Andrew Waterman1-1/+2
2019-11-20Add pass-through interrupt support and hgeie/hgeip registersAndrew Waterman1-0/+2
2019-11-06Hypervisor tweaksAndrew Waterman1-2/+2
2019-11-05Improve commentary environment page-break behaviorAndrew Waterman1-1/+0
2019-10-29hypervisor draft v0.5Andrew Waterman1-0/+9
2019-08-21Use RV32 consistently in the CSR listingColumbus2401-12/+12
2019-08-21Remove trailing whitespace from priv-csrs.texColumbus2401-34/+34
2019-08-20Fix typo in hcounteren privilegeAndrew Waterman1-1/+1
2019-08-16hypervisor: add performance counter delta registersPaolo Bonzini1-0/+5
2019-07-21Move N extension into its own chapter in the priv specAndrew Waterman1-0/+1
2019-06-19Add endianness control proposal to priv specAndrew Waterman1-0/+1
2019-06-16Hypervisor v0.4 draftAndrew Waterman1-14/+15
2019-04-05Privileged Spec: Add dscratch0/1 to CSR listing (#361)Philipp Wagner1-1/+2
2019-03-12Reformat CSR address map tableAndrew Waterman1-29/+39
2019-01-21Add hypervisor CSR listingAndrew Waterman1-43/+42
2018-12-04Debug registers 7A0-7AF are accessible to M-modeAndrew Waterman1-3/+5
2018-12-04Version of priv spec ready for ratification processAndrew Waterman1-6/+10
2018-12-02Non-standard -> customAndrew Waterman1-35/+23
2018-11-27Misc. address translation clarificationsAndrew Waterman1-1/+1
2018-11-21Add counter-inhibit mechanismAndrew Waterman1-0/+1
2018-11-20Fix colliding labelsAndrew Waterman1-3/+3
2018-09-23No need for WIRI definition anymoreAndrew Waterman1-11/+0
2018-04-13Remove hyphen from M-XLEN etc.Andrew Waterman1-1/+1
2018-04-13Clarifications re: writable XLENAndrew Waterman1-0/+28
2017-12-28WIRI/WPRI fields should be hardwired to 0 (#121)Andrew Waterman1-4/+8
2017-11-12Clarify WLRL semanticsAndrew Waterman1-1/+1
2017-04-11SPTBR -> SATPAndrew Waterman1-1/+1
2017-03-30Update PMP CSR listingAndrew Waterman1-4/+8
2017-03-28Renamed mbadbits to mtval (for "Trap Value") to be more generic name for regi...Krste Asanovic1-4/+4
2017-03-26Replaced mbadaddr with mbadbits register, which can now capture badKrste Asanovic1-4/+4
2017-03-20Removed explicit convention on shadow CSRs.Krste Asanovic1-16/+23
2017-03-19Excised H-mode from spec.Krste Asanovic1-40/+43
2017-02-26Incorporate more Hauser feedbackAndrew Waterman1-10/+10
2017-02-21Move counter-enable CSRs to trap-setup CSR spaceAndrew Waterman1-9/+3
2017-02-20mhcounteren -> mcounteren; mucounteren -> scounterenAndrew Waterman1-3/+9
2017-02-01Reorganize directory structureAndrew Waterman1-0/+421
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