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AgeCommit message (Expand)AuthorFilesLines
2021-09-15RISC-V Foundation -> RISC-V InternationalAndrew Waterman1-5/+5
2021-09-15mip.MSIP and mie.MSIE may be hardwired zeros (#738)John Hauser1-0/+4
2021-09-14Fix apparent typo re hpmcounter*h (#735)Scott Johnson1-1/+1
2021-09-14State behavior of uncacheable accesses to cacheable locationsAndrew Waterman1-0/+13
2021-09-14Clarify that WARL fields contain legal values after reset (#734)Andrew Waterman1-0/+1
2021-09-11Rename STCE to STCD to reverse its polarityAndrew Waterman1-2/+2
2021-09-10Generalize SSIP to support forthcoming interrupt controllers (#726)Andrew Waterman1-18/+2
2021-09-10Speculative implicit reads, v2 (#724)Andrew Waterman1-0/+15
2021-09-08Merge pull request #727 from riscv/mseccfgAndrew Waterman1-0/+157
2021-09-08FIOM may be hardwired when satp is hardwiredAndrew Waterman1-1/+2
2021-09-02Describe purpose of FIOM mechanismAndrew Waterman1-0/+6
2021-09-02Pedantically clarify behavior of writing lo/hi parts of countersAndrew Waterman1-4/+5
2021-09-01FIOM may optionally not exist in M/U systemsAndrew Waterman1-0/+2
2021-08-30Fix constraint on existence of menvcfg[h]/FIOMAndrew Waterman1-2/+3
2021-08-29FIOM affects aq/rl, tooAndrew Waterman1-0/+6
2021-08-29Add henvcfg/senvcfg CSRsAndrew Waterman1-0/+92
2021-08-29Add mseccfg CSRAndrew Waterman1-0/+49
2021-08-29Designate some of SYSTEM opcode for custom useAndrew Waterman1-0/+40
2021-08-28Add mconfigptr CSR (#697)Andrew Waterman1-0/+46
2021-08-25Remove historical remark on MRET definitionAndrew Waterman1-9/+0
2021-08-18Tweak table of synchronous exception priorities (#716)John Hauser1-5/+6
2021-08-17Clarify priorities of synchronous exceptions (#715)John Hauser1-14/+30
2021-08-13Clarify when mstatus.FS may be hardwired zero (#707)John Hauser1-3/+5
2021-08-11Interrupt conditions are also evaluated on falling edgesAndrew Waterman1-1/+2
2021-08-11Generalize interrupt trap condition evaluation conditions (#705)Andrew Waterman1-1/+3
2021-08-11Clarify that RV64 accesses to mtime[cmp] are atomicAndrew Waterman1-1/+1
2021-08-11State that misa.F does not affect mstatus.FSAndrew Waterman1-2/+13
2021-08-06Clarify mepc invalid address conversionAndrew Waterman1-4/+6
2021-08-05Improve description of interrupt traps (#701)Andrew Waterman1-18/+18
2021-07-22Resolve contradiction in mtval definition (#685)Andrew Waterman1-7/+11
2021-07-22mstatush is not optional in priv-1.12 (#683)Andrew Waterman1-3/+0
2021-07-13Remove or downgrade more references to N extension (#674)John Hauser1-6/+5
2021-07-03CSR instead of field (#669)Iztok Jeras1-1/+1
2021-06-12Remove concept of hard reset from normative textAndrew Waterman1-1/+1
2021-06-08PMP RWX are collectively WARL, with R=0 W=1 being illegal (#658)Andrew Waterman1-3/+4
2021-06-04Remove T placeholder chapterAndrew Waterman1-1/+1
2021-06-03Remove L placeholder chapter from specAndrew Waterman1-1/+1
2021-05-25Use plural "base ISAs" rather than "base ISA" when appropriateAndrew Waterman1-1/+1
2021-04-23Minor mstatus and sstatus layout edits. (#642)Steven Bellock1-54/+53
2021-04-21SUM should be hardwired to 0 for cores without paging (#641)Andrew Waterman1-1/+1
2021-02-10Clarify type of timer interrupt (#617)Bartek Gąsiorzewski1-1/+1
2021-02-10Fix editing error introduced in 9ff515cd6695ac392e5ca32b73a135aa197e2778Andrew Waterman1-1/+1
2021-01-13Explain rationale for seting xPP=U on an xRETAndrew Waterman1-1/+7
2021-01-13Clean up NMI/mepc wordingAndrew Waterman1-2/+2
2021-01-12Additional FS clarificationAndrew Waterman1-1/+1
2021-01-12spell checkAndrew Waterman1-1/+1
2021-01-12clarify that FS need only be set to dirty if the state is actually changedAndrew Waterman1-0/+4
2020-12-22Make unused misa fields 0 (WARL) rather than WLRL. (#615)Paul Donahue1-1/+1
2020-11-19Dedicated section for machine-level memory-mapped registers (not standard CSR...Alexandre Joannou1-114/+116
2020-11-06PMP uses physical addresses (not effective addresses) (#610)Paul Donahue1-2/+2
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