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riscv-isa-manual.git
1437-update-generated-filenames-to-be-more-desciptive
1454-fix-merge-and-release-workflow
1532-lack-of-list-of-figures-tables
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Svinval
Svnapot
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antora-refactor
aswaterman-patch-1
atomics-wording-v2
bonzini-hpmdelta
cnop
convert2adoc_rvwmo
csr-wip
dev/beeman/smctr-ssctr
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hypervisor
kersten1-patch-3
latex
lrsc
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misa-ztso
msip
mtime-optional
n-ext
pmp
ratified-priv-v1.11-sans-hypervisor-draft
sail-inclusion-example
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v20240411
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Author
Files
Lines
2021-09-15
RISC-V Foundation -> RISC-V International
Andrew Waterman
1
-5
/
+5
2021-09-15
mip.MSIP and mie.MSIE may be hardwired zeros (#738)
John Hauser
1
-0
/
+4
2021-09-14
Fix apparent typo re hpmcounter*h (#735)
Scott Johnson
1
-1
/
+1
2021-09-14
State behavior of uncacheable accesses to cacheable locations
Andrew Waterman
1
-0
/
+13
2021-09-14
Clarify that WARL fields contain legal values after reset (#734)
Andrew Waterman
1
-0
/
+1
2021-09-11
Rename STCE to STCD to reverse its polarity
Andrew Waterman
1
-2
/
+2
2021-09-10
Generalize SSIP to support forthcoming interrupt controllers (#726)
Andrew Waterman
1
-18
/
+2
2021-09-10
Speculative implicit reads, v2 (#724)
Andrew Waterman
1
-0
/
+15
2021-09-08
Merge pull request #727 from riscv/mseccfg
Andrew Waterman
1
-0
/
+157
2021-09-08
FIOM may be hardwired when satp is hardwired
Andrew Waterman
1
-1
/
+2
2021-09-02
Describe purpose of FIOM mechanism
Andrew Waterman
1
-0
/
+6
2021-09-02
Pedantically clarify behavior of writing lo/hi parts of counters
Andrew Waterman
1
-4
/
+5
2021-09-01
FIOM may optionally not exist in M/U systems
Andrew Waterman
1
-0
/
+2
2021-08-30
Fix constraint on existence of menvcfg[h]/FIOM
Andrew Waterman
1
-2
/
+3
2021-08-29
FIOM affects aq/rl, too
Andrew Waterman
1
-0
/
+6
2021-08-29
Add henvcfg/senvcfg CSRs
Andrew Waterman
1
-0
/
+92
2021-08-29
Add mseccfg CSR
Andrew Waterman
1
-0
/
+49
2021-08-29
Designate some of SYSTEM opcode for custom use
Andrew Waterman
1
-0
/
+40
2021-08-28
Add mconfigptr CSR (#697)
Andrew Waterman
1
-0
/
+46
2021-08-25
Remove historical remark on MRET definition
Andrew Waterman
1
-9
/
+0
2021-08-18
Tweak table of synchronous exception priorities (#716)
John Hauser
1
-5
/
+6
2021-08-17
Clarify priorities of synchronous exceptions (#715)
John Hauser
1
-14
/
+30
2021-08-13
Clarify when mstatus.FS may be hardwired zero (#707)
John Hauser
1
-3
/
+5
2021-08-11
Interrupt conditions are also evaluated on falling edges
Andrew Waterman
1
-1
/
+2
2021-08-11
Generalize interrupt trap condition evaluation conditions (#705)
Andrew Waterman
1
-1
/
+3
2021-08-11
Clarify that RV64 accesses to mtime[cmp] are atomic
Andrew Waterman
1
-1
/
+1
2021-08-11
State that misa.F does not affect mstatus.FS
Andrew Waterman
1
-2
/
+13
2021-08-06
Clarify mepc invalid address conversion
Andrew Waterman
1
-4
/
+6
2021-08-05
Improve description of interrupt traps (#701)
Andrew Waterman
1
-18
/
+18
2021-07-22
Resolve contradiction in mtval definition (#685)
Andrew Waterman
1
-7
/
+11
2021-07-22
mstatush is not optional in priv-1.12 (#683)
Andrew Waterman
1
-3
/
+0
2021-07-13
Remove or downgrade more references to N extension (#674)
John Hauser
1
-6
/
+5
2021-07-03
CSR instead of field (#669)
Iztok Jeras
1
-1
/
+1
2021-06-12
Remove concept of hard reset from normative text
Andrew Waterman
1
-1
/
+1
2021-06-08
PMP RWX are collectively WARL, with R=0 W=1 being illegal (#658)
Andrew Waterman
1
-3
/
+4
2021-06-04
Remove T placeholder chapter
Andrew Waterman
1
-1
/
+1
2021-06-03
Remove L placeholder chapter from spec
Andrew Waterman
1
-1
/
+1
2021-05-25
Use plural "base ISAs" rather than "base ISA" when appropriate
Andrew Waterman
1
-1
/
+1
2021-04-23
Minor mstatus and sstatus layout edits. (#642)
Steven Bellock
1
-54
/
+53
2021-04-21
SUM should be hardwired to 0 for cores without paging (#641)
Andrew Waterman
1
-1
/
+1
2021-02-10
Clarify type of timer interrupt (#617)
Bartek GÄ…siorzewski
1
-1
/
+1
2021-02-10
Fix editing error introduced in 9ff515cd6695ac392e5ca32b73a135aa197e2778
Andrew Waterman
1
-1
/
+1
2021-01-13
Explain rationale for seting xPP=U on an xRET
Andrew Waterman
1
-1
/
+7
2021-01-13
Clean up NMI/mepc wording
Andrew Waterman
1
-2
/
+2
2021-01-12
Additional FS clarification
Andrew Waterman
1
-1
/
+1
2021-01-12
spell check
Andrew Waterman
1
-1
/
+1
2021-01-12
clarify that FS need only be set to dirty if the state is actually changed
Andrew Waterman
1
-0
/
+4
2020-12-22
Make unused misa fields 0 (WARL) rather than WLRL. (#615)
Paul Donahue
1
-1
/
+1
2020-11-19
Dedicated section for machine-level memory-mapped registers (not standard CSR...
Alexandre Joannou
1
-114
/
+116
2020-11-06
PMP uses physical addresses (not effective addresses) (#610)
Paul Donahue
1
-2
/
+2
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