riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-04-15	Update CSR access ordering section to clarify ordering is two-sided	Andrew Waterman	1	-8/+10
2019-03-24	Improve CSR ordering section	Andrew Waterman	1	-29/+44
2019-03-14	memory -> main memory	Andrew Waterman	1	-1/+1
2019-03-13	Improve commentary on CSR ordering	Andrew Waterman	1	-5/+8
2019-03-13	Revise CSR-ordering section	Andrew Waterman	1	-6/+22
2019-03-12	Clarify that CSR accesses can be ordered with FENCEs	Andrew Waterman	1	-0/+17
2019-02-07	Fix typos. (#337)	Josh Scheid	1	-3/+3
2018-11-19	Remove comment about side effects on writes	Andrew Waterman	1	-4/+3
2018-11-16	Clarified behavior of CSR instructions with respect to read and write side ef...	Krste Asanovic	1	-4/+48
2018-11-06	Gave CSR instruction module a name and a version, and made clear these are be...	Krste Asanovic	1	-1/+1
2018-08-26	Clarified description of CSR writes to counters per Nikhil's suggestion.	Krste Asanovic	1	-8/+7
2018-08-07	Broke out actual perf counters into separate chapter.	Krste Asanovic	1	-178/+15
2018-08-06	CSR instructions file.	Krste Asanovic	1	-0/+277