riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-01-17	Removing tex files.	Bill Traynor	1	-260/+0
2022-07-26	Fix typo	Andrew Waterman	1	-1/+1
2021-08-27	Fix (again) non-normative CSR side-effect text	Andrew Waterman	1	-2/+1
2021-08-24	Fix non-normative text about CSR ordering (#720)	Andrew Waterman	1	-9/+12
2021-07-22	Standard CSRs don't have read side effects (#687)	Andrew Waterman	1	-3/+5
2021-05-25	Use plural "base ISAs" rather than "base ISA" when appropriate	Andrew Waterman	1	-1/+1
2020-08-14	Improve table of conditions for explicit CSR read/write (#564)	John Hauser	1	-15/+18
2020-08-13	Merge pull request #547 from jhauser-us/jhauser-CSRSideEffects3	Andrew Waterman	1	-0/+25
2020-08-13	Merge pull request #531 from jhauser-us/jhauser-CSRRules	Andrew Waterman	1	-15/+28
2020-07-30	Further clarified the program order of CSR accesses	John Hauser	1	-4/+10
2020-07-27	Clarify effect on unwritten bits for CSRRS/CSRRC	Andrew Waterman	1	-4/+3
2020-07-23	Add examples for CSR side effects and indirect effects	John Hauser	1	-0/+25
2020-07-22	Clarify what is a side effect of a CSR access (#546)	John Hauser	1	-7/+14
2020-06-28	Clarifications to the perceived ordering of CSR accesses and their effects	John Hauser	1	-13/+20
2019-04-15	Update CSR access ordering section to clarify ordering is two-sided	Andrew Waterman	1	-8/+10
2019-03-24	Improve CSR ordering section	Andrew Waterman	1	-29/+44
2019-03-14	memory -> main memory	Andrew Waterman	1	-1/+1
2019-03-13	Improve commentary on CSR ordering	Andrew Waterman	1	-5/+8
2019-03-13	Revise CSR-ordering section	Andrew Waterman	1	-6/+22
2019-03-12	Clarify that CSR accesses can be ordered with FENCEs	Andrew Waterman	1	-0/+17
2019-02-07	Fix typos. (#337)	Josh Scheid	1	-3/+3
2018-11-19	Remove comment about side effects on writes	Andrew Waterman	1	-4/+3
2018-11-16	Clarified behavior of CSR instructions with respect to read and write side ef...	Krste Asanovic	1	-4/+48
2018-11-06	Gave CSR instruction module a name and a version, and made clear these are be...	Krste Asanovic	1	-1/+1
2018-08-26	Clarified description of CSR writes to counters per Nikhil's suggestion.	Krste Asanovic	1	-8/+7
2018-08-07	Broke out actual perf counters into separate chapter.	Krste Asanovic	1	-178/+15
2018-08-06	CSR instructions file.	Krste Asanovic	1	-0/+277