| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-11-10 | Add marchid for Fraunhofer-IMS AIRISC (#913) | stnolting | 1 | -0/+1 | |
| Signed-off-by: stnolting-ims <117631738+stnolting-ims@users.noreply.github.com> Signed-off-by: stnolting-ims <117631738+stnolting-ims@users.noreply.github.com> | |||||
| 2022-09-10 | Add RISu064 to open-source marchid list (#892) | Wenting Zhang | 1 | -0/+1 | |
| 2022-07-15 | Add marchid for Rift (#871) | Ruige Lee | 1 | -0/+1 | |
| Signed-off-by: Ruige Lee <295054118@whut.edu.cn> | |||||
| 2022-04-04 | Fix BOOM URL | Andrew Waterman | 1 | -1/+1 | |
| Resolves #833 | |||||
| 2022-02-17 | rocket-chip is hosted at chipsalliance, not freechipsproject | Andrew Waterman | 1 | -1/+1 | |
| 2022-02-17 | Adds CV32E41P to MARCHID (#818) | Ibrahim Abu Kharmeh | 1 | -0/+1 | |
| Adds [CV32E41P ]https://github.com/openhwgroup/cv32e41p to the MARCHID list. The core started its life as a fork of the CV32E40P core to implement the official RISC-V [Zfinx](https://github.com/riscv/riscv-zfinx/blob/main/zfinx-spec-20210511-0.41.pdf) and [Zce](https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.50.1-TOOLCHAIN-DEV) ISA extensions. Closes https://github.com/openhwgroup/cv32e41p/issues/7 | |||||
| 2021-11-28 | Add Hazard3 to open-source marchid list (#784) | Luke Wren | 1 | -0/+1 | |
| This is a 3-stage `RV32I` core, with optional support for `M`/`C`/`Zba`/`Zbb`/`Zbc`/`Zbs` and debug support. It passes the ISA compliance tests, riscv-formal, OpenOCD DM compliance tests and the end-to-end debug tests from riscv-tests/debug. [Github](https://github.com/Wren6991/Hazard3/blob/master/License) [PDF documentation](https://github.com/Wren6991/Hazard3/blob/master/doc/hazard3.pdf) The license is DWTFPLv3, which is effectively a public domain dedication. | |||||
| 2021-08-24 | Add marchid for Hummingbirdv2 E203 (#664) | hucan7 | 1 | -1/+1 | |
| 2021-06-10 | Add marchid for XiangShan (#661) | Yinan Xu | 1 | -0/+2 | |
| 2021-06-01 | Steel Core marchid added | Rafael Calcada | 1 | -0/+1 | |
| 2021-05-01 | marchid request for RudolV (#643) | Jörg Mische | 1 | -0/+1 | |
| 2021-04-13 | Requesting marchid for cv32e40x and cv32e40s (#630) | Arjan Bink | 1 | -0/+2 | |
| Signed-off-by: Arjan Bink <Arjan.Bink@silabs.com> Co-authored-by: Andrew Waterman <andrew@sifive.com> | |||||
| 2021-04-13 | marchid request for Ibex (#638) | Greg Chadwick | 1 | -0/+1 | |
| 2020-10-12 | marchid request for NEORV32 core (#579)pause-public-review-20201013 | Stephan | 1 | -0/+1 | |
| 2020-09-11 | update OpenHW cores (#578) | Pasquale Davide Schiavone | 1 | -2/+2 | |
| 2020-08-20 | Add marchid for SERV (#569) | Olof Kindgren | 1 | -0/+1 | |
| 2020-01-09 | Add Western Digital's SweRV EL2 and EH2 cores (#474) | Thomas Wicki | 1 | -0/+2 | |
| Western Digital's second generation cores SweRV EL2 and EH2 | |||||
| 2019-09-10 | marchid for c-class core of SHAKTI (#448) | Neel Gala | 1 | -0/+1 | |
| 2019-07-12 | Update SweRV project URL (#408) | Thomas Wicki | 1 | -1/+1 | |
| 2019-06-21 | add BlackParrot and BaseJump Manycore (#396) | black-parrot | 1 | -0/+2 | |
| 2019-03-01 | Update marchid.md (#346) | Rongcui Dong | 1 | -0/+1 | |
| 2019-01-24 | Change SweRV EH1 URL (#330) | tmw-wdc | 1 | -1/+1 | |
| 2019-01-23 | Change contact for SweRV EH1 (#329) | tmw-wdc | 1 | -1/+1 | |
| * Update marchid.md Add Western Digital's SweRV EH1 * Update marchid.md Changed contact for SweRV EH1 | |||||
| 2019-01-16 | Update marchid.md (#325) | tmw-wdc | 1 | -0/+1 | |
| Add Western Digital's SweRV EH1 | |||||
| 2018-12-03 | Adding an marchid for the RVBS open source project (#292) | Alexandre Joannou | 1 | -1/+2 | |
| 2018-11-07 | Register YARVI's machid (#260) | Tommy Thorn | 1 | -0/+1 | |
| 2018-11-07 | Update marchid.md (#256) | Dmitri Pavlov | 1 | -0/+1 | |
| 2018-11-07 | Update marchid.md for VectorBlox ORCA (#253) | vbx-glemieux | 1 | -0/+1 | |
| 2018-11-07 | Revert "Update marchid.md (#254)" | Andrew Waterman | 1 | -2/+0 | |
| This reverts commit 327be43b7907645c6a63876f1064008dcfda1b43. | |||||
| 2018-11-07 | Update marchid.md (#254) | Dmitri Pavlov | 1 | -0/+2 | |
| 2018-11-04 | Adding SHAKTI's E-Class to marchid list (#250) | Neel Gala | 1 | -0/+1 | |
| 2018-10-06 | Add PULP cores to marchid.md (#236) | Florian Zaruba | 1 | -6/+8 | |
| * Add Ariane to marchid * Add RI5CY to marchid.md | |||||
| 2018-10-04 | Update marchid.md. (#235) | Christopher Celio | 1 | -0/+1 | |
| Add BOOM. | |||||
| 2018-10-04 | Allocate Spike marchid | Andrew Waterman | 1 | -0/+1 | |
| 2018-10-04 | Add marchid management document (#234) | Andrew Waterman | 1 | -0/+21 | |
| * Fix broken link * Add marchid document | |||||
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index : riscv-isa-manual.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |
path: root/marchid.md