Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2020-08-23 | Clarify description of CB format | Andrew Waterman | 1 | -2/+2 | |
Resolves #570 | |||||
2020-08-20 | Add marchid for SERV (#569) | Olof Kindgren | 1 | -0/+1 | |
2020-08-18 | Remove assembly manual | Andrew Waterman | 4 | -168/+10 | |
It is to be migrated to https://github.com/riscv/riscv-asm-manual See #540 | |||||
2020-08-14 | Change "reserved for custom" to "designated for custom" (#566) | John Hauser | 9 | -30/+30 | |
2020-08-14 | Improve table of conditions for explicit CSR read/write (#564) | John Hauser | 1 | -15/+18 | |
2020-08-14 | Improve table of RAS hints for JALR instructions (#563) | John Hauser | 1 | -10/+11 | |
2020-08-14 | Improve table of trap characteristics in introduction (#562) | John Hauser | 1 | -6/+8 | |
2020-08-13 | Merge pull request #547 from jhauser-us/jhauser-CSRSideEffects3 | Andrew Waterman | 1 | -0/+25 | |
Add examples for CSR side effects and indirect effects | |||||
2020-08-13 | Merge pull request #531 from jhauser-us/jhauser-CSRRules | Andrew Waterman | 1 | -15/+28 | |
Clarifications to the perceived ordering of CSR accesses and their effects | |||||
2020-08-12 | mcounteren only exists if U-mode exists | Andrew Waterman | 1 | -0/+2 | |
Resolves #561 | |||||
2020-08-03 | Fix formatting of 2^XLEN | Andrew Waterman | 3 | -9/+9 | |
h/t Trond Endrestøl | |||||
2020-07-31 | Add missing word | Andrew Waterman | 1 | -1/+1 | |
2020-07-31 | Clarify that ASID changes are also immediate | Andrew Waterman | 1 | -0/+1 | |
2020-07-31 | Clarify that satp.MODE transitions to/from Bare don't require SFENCE.VMA | Andrew Waterman | 1 | -0/+3 | |
Resolves #538 | |||||
2020-07-31 | Reserve some satp encodings for custom use | Andrew Waterman | 1 | -5/+11 | |
2020-07-30 | Fix Sv48 VALEN typo (#551) | Daniel Lustig | 1 | -1/+1 | |
2020-07-30 | Further clarified the program order of CSR accesses | John Hauser | 1 | -4/+10 | |
2020-07-27 | Clarify effect on unwritten bits for CSRRS/CSRRC | Andrew Waterman | 1 | -4/+3 | |
They aren't _explicitly_ written, but that doesn't mean they are unaffected, since they could change as a result of the bits that are written. Resolves #549 | |||||
2020-07-26 | Clarify which implicit reads of the translation structures are allowed | Andrew Waterman | 1 | -1/+2 | |
2020-07-25 | tweak | Andrew Waterman | 1 | -1/+1 | |
We don't define "soft page fault" anywhere, so just use "page fault", which is also correct. | |||||
2020-07-25 | Add commentary about caching invalid PTEs | Andrew Waterman | 1 | -0/+7 | |
2020-07-23 | Add examples for CSR side effects and indirect effects | John Hauser | 1 | -0/+25 | |
2020-07-22 | Clarify what is a side effect of a CSR access (#546) | John Hauser | 1 | -7/+14 | |
2020-07-22 | Pmp wording fix (#545) | Stef O'Rear | 6 | -25/+26 | |
* Consistently use "access-fault exception" for PMPs Except for discussions of the xcause code itself which are "access fault". * Clarify behavior of locked TOR PMPs | |||||
2020-07-20 | clarify that high counters are RV32I-only | Andrew Waterman | 1 | -1/+1 | |
2020-07-20 | Make it explicit that the priv arch requires Zicsr | Andrew Waterman | 1 | -3/+9 | |
2020-07-19 | Add missing word | Andrew Waterman | 1 | -1/+1 | |
The RDTIMEH and RDINSTRETH are described as RV32I-only instructions, but RDCYCLEH was mistakenly described as RV32I rather than RV32I-only. | |||||
2020-07-17 | Remove redundant phrase from access-/page-fault text | Andrew Waterman | 2 | -2/+2 | |
Resolves #542 | |||||
2020-06-28 | Clarifications to the perceived ordering of CSR accesses and their effects | John Hauser | 1 | -13/+20 | |
More clearly distinguished the ordering rules that apply to the same hart from those that involve other agents (harts and devices). Made CSR side effects completely synchronous to the same hart by default. (Deviances are still allowed, when documented.) Added a comment that rules about the reordering of CSR accesses in the global memory order should probably be moved to the RVWMO chapter. | |||||
2020-06-10 | Fix preface | Andrew Waterman | 1 | -2/+2 | |
2020-06-10 | Priority of misaligned load/store address checks is implementation-defined | Andrew Waterman | 2 | -1/+21 | |
2020-06-04 | FADD/FSUB can't raise UF, hence, no PPO dependence | Andrew Waterman | 1 | -4/+4 | |
Resolves #527 | |||||
2020-06-04 | Fix unclarity in MPRV definition introduced by ↵ | Andrew Waterman | 1 | -1/+1 | |
569d07195a8495460f04592d8455153f730a0f54 Resolves #528 | |||||
2020-05-31 | Merge pull request #525 from riscv/64-pmp-entries | Andrew Waterman | 3 | -28/+51 | |
Extend PMP scheme to support 64 regions | |||||
2020-05-22 | Extend PMP scheme to support 64 regions | Andrew Waterman | 3 | -28/+51 | |
2020-05-21 | Merge pull request #523 from jhauser-us/jhauser-hstatusVTW | Andrew Waterman | 1 | -21/+14 | |
Add VTW field to hstatus; improve rules for WFI in virtual modes | |||||
2020-05-18 | Clarify that satp.MODE=Bare with satp.LSBs != 0 is unspecified for now | Andrew Waterman | 1 | -0/+3 | |
2020-05-14 | Add VTW field to hstatus; improve rules for WFI in virtual modes | John Hauser | 1 | -21/+14 | |
Add (restore) field VTW to CSR hstatus, analogous to mstatus.TW. Also, better clarify the rules for the exceptions raised by instruction WFI when in virtual operating modes (VS mode and VU mode). | |||||
2020-05-14 | Merge pull request #518 from jhauser-us/jhauser-virtualinstexception | Andrew Waterman | 1 | -13/+90 | |
Add virtual instruction exceptions to the hypervisor extension | |||||
2020-05-13 | Expand the circumstances that raise virtual instruction exceptions | John Hauser | 1 | -18/+20 | |
Expand the set of circumstances that raise virtual instruction exceptions instead of illegal instruction exceptions. | |||||
2020-05-11 | Improve description of RV64 *W instructions | Andrew Waterman | 1 | -7/+8 | |
2020-05-05 | Clarify that _coherent_ main memory regions use RVWMO or RVTSO | Andrew Waterman | 1 | -2/+4 | |
2020-05-05 | Add virtual instruction exceptions to the hypervisor extension | John Hauser | 1 | -12/+87 | |
For the hypervisor extension, add another exception type, "virtual instruction exception", that substitutes for the illegal instruction exception in cases where a hypervisor is expected to emulate the instruction. This saves time because this exception type can be delegated directly to HS mode, whereas illegal instructions will typically be processed first in M mode and delegated to HS mode only by software. | |||||
2020-04-23 | Clarify semantics of sfence.vma with rs1 != 0 (#515) | Jonathan Behrens | 1 | -2/+2 | |
Based on discussion on the mailing list, the instruction fences accesses not just to one leaf PTE but to any leaf PTE that includes the address (subject to address space constraints specified via rs2). | |||||
2020-04-22 | Clarify that mtimecmp comparison is unsigned | Andrew Waterman | 1 | -3/+4 | |
2020-04-22 | Clarify that various reset events are relative to hart reset | Andrew Waterman | 1 | -4/+4 | |
2020-04-17 | Clarify that RV64 accesses to mtime/mtimecmp are atomic | Andrew Waterman | 1 | -0/+3 | |
2020-04-16 | Make misaligned exception text more generic than RV32 | Andrew Waterman | 1 | -3/+3 | |
2020-04-16 | Clarify that the EEI defines misaligned FP ld/st behavior | Andrew Waterman | 2 | -0/+5 | |
2020-04-14 | Avoid "should" when describing a mandate | Andrew Waterman | 1 | -2/+2 | |
Resolves #510 |