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2020-08-23Clarify description of CB formatAndrew Waterman1-2/+2
Resolves #570
2020-08-20Add marchid for SERV (#569)Olof Kindgren1-0/+1
2020-08-18Remove assembly manualAndrew Waterman4-168/+10
It is to be migrated to https://github.com/riscv/riscv-asm-manual See #540
2020-08-14Change "reserved for custom" to "designated for custom" (#566)John Hauser9-30/+30
2020-08-14Improve table of conditions for explicit CSR read/write (#564)John Hauser1-15/+18
2020-08-14Improve table of RAS hints for JALR instructions (#563)John Hauser1-10/+11
2020-08-14Improve table of trap characteristics in introduction (#562)John Hauser1-6/+8
2020-08-13Merge pull request #547 from jhauser-us/jhauser-CSRSideEffects3Andrew Waterman1-0/+25
Add examples for CSR side effects and indirect effects
2020-08-13Merge pull request #531 from jhauser-us/jhauser-CSRRulesAndrew Waterman1-15/+28
Clarifications to the perceived ordering of CSR accesses and their effects
2020-08-12mcounteren only exists if U-mode existsAndrew Waterman1-0/+2
Resolves #561
2020-08-03Fix formatting of 2^XLENAndrew Waterman3-9/+9
h/t Trond Endrestøl
2020-07-31Add missing wordAndrew Waterman1-1/+1
2020-07-31Clarify that ASID changes are also immediateAndrew Waterman1-0/+1
2020-07-31Clarify that satp.MODE transitions to/from Bare don't require SFENCE.VMAAndrew Waterman1-0/+3
Resolves #538
2020-07-31Reserve some satp encodings for custom useAndrew Waterman1-5/+11
2020-07-30Fix Sv48 VALEN typo (#551)Daniel Lustig1-1/+1
2020-07-30Further clarified the program order of CSR accessesJohn Hauser1-4/+10
2020-07-27Clarify effect on unwritten bits for CSRRS/CSRRCAndrew Waterman1-4/+3
They aren't _explicitly_ written, but that doesn't mean they are unaffected, since they could change as a result of the bits that are written. Resolves #549
2020-07-26Clarify which implicit reads of the translation structures are allowedAndrew Waterman1-1/+2
2020-07-25tweakAndrew Waterman1-1/+1
We don't define "soft page fault" anywhere, so just use "page fault", which is also correct.
2020-07-25Add commentary about caching invalid PTEsAndrew Waterman1-0/+7
2020-07-23Add examples for CSR side effects and indirect effectsJohn Hauser1-0/+25
2020-07-22Clarify what is a side effect of a CSR access (#546)John Hauser1-7/+14
2020-07-22Pmp wording fix (#545)Stef O'Rear6-25/+26
* Consistently use "access-fault exception" for PMPs Except for discussions of the xcause code itself which are "access fault". * Clarify behavior of locked TOR PMPs
2020-07-20clarify that high counters are RV32I-onlyAndrew Waterman1-1/+1
2020-07-20Make it explicit that the priv arch requires ZicsrAndrew Waterman1-3/+9
2020-07-19Add missing wordAndrew Waterman1-1/+1
The RDTIMEH and RDINSTRETH are described as RV32I-only instructions, but RDCYCLEH was mistakenly described as RV32I rather than RV32I-only.
2020-07-17Remove redundant phrase from access-/page-fault textAndrew Waterman2-2/+2
Resolves #542
2020-06-28Clarifications to the perceived ordering of CSR accesses and their effectsJohn Hauser1-13/+20
More clearly distinguished the ordering rules that apply to the same hart from those that involve other agents (harts and devices). Made CSR side effects completely synchronous to the same hart by default. (Deviances are still allowed, when documented.) Added a comment that rules about the reordering of CSR accesses in the global memory order should probably be moved to the RVWMO chapter.
2020-06-10Fix prefaceAndrew Waterman1-2/+2
2020-06-10Priority of misaligned load/store address checks is implementation-definedAndrew Waterman2-1/+21
2020-06-04FADD/FSUB can't raise UF, hence, no PPO dependenceAndrew Waterman1-4/+4
Resolves #527
2020-06-04Fix unclarity in MPRV definition introduced by ↵Andrew Waterman1-1/+1
569d07195a8495460f04592d8455153f730a0f54 Resolves #528
2020-05-31Merge pull request #525 from riscv/64-pmp-entriesAndrew Waterman3-28/+51
Extend PMP scheme to support 64 regions
2020-05-22Extend PMP scheme to support 64 regionsAndrew Waterman3-28/+51
2020-05-21Merge pull request #523 from jhauser-us/jhauser-hstatusVTWAndrew Waterman1-21/+14
Add VTW field to hstatus; improve rules for WFI in virtual modes
2020-05-18Clarify that satp.MODE=Bare with satp.LSBs != 0 is unspecified for nowAndrew Waterman1-0/+3
2020-05-14Add VTW field to hstatus; improve rules for WFI in virtual modesJohn Hauser1-21/+14
Add (restore) field VTW to CSR hstatus, analogous to mstatus.TW. Also, better clarify the rules for the exceptions raised by instruction WFI when in virtual operating modes (VS mode and VU mode).
2020-05-14Merge pull request #518 from jhauser-us/jhauser-virtualinstexceptionAndrew Waterman1-13/+90
Add virtual instruction exceptions to the hypervisor extension
2020-05-13Expand the circumstances that raise virtual instruction exceptionsJohn Hauser1-18/+20
Expand the set of circumstances that raise virtual instruction exceptions instead of illegal instruction exceptions.
2020-05-11Improve description of RV64 *W instructionsAndrew Waterman1-7/+8
2020-05-05Clarify that _coherent_ main memory regions use RVWMO or RVTSOAndrew Waterman1-2/+4
2020-05-05Add virtual instruction exceptions to the hypervisor extensionJohn Hauser1-12/+87
For the hypervisor extension, add another exception type, "virtual instruction exception", that substitutes for the illegal instruction exception in cases where a hypervisor is expected to emulate the instruction. This saves time because this exception type can be delegated directly to HS mode, whereas illegal instructions will typically be processed first in M mode and delegated to HS mode only by software.
2020-04-23Clarify semantics of sfence.vma with rs1 != 0 (#515)Jonathan Behrens1-2/+2
Based on discussion on the mailing list, the instruction fences accesses not just to one leaf PTE but to any leaf PTE that includes the address (subject to address space constraints specified via rs2).
2020-04-22Clarify that mtimecmp comparison is unsignedAndrew Waterman1-3/+4
2020-04-22Clarify that various reset events are relative to hart resetAndrew Waterman1-4/+4
2020-04-17Clarify that RV64 accesses to mtime/mtimecmp are atomicAndrew Waterman1-0/+3
2020-04-16Make misaligned exception text more generic than RV32Andrew Waterman1-3/+3
2020-04-16Clarify that the EEI defines misaligned FP ld/st behaviorAndrew Waterman2-0/+5
2020-04-14Avoid "should" when describing a mandateAndrew Waterman1-2/+2
Resolves #510
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