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| author | Jonathan Behrens <fintelia@gmail.com> | 2020-04-23 23:30:46 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-23 20:30:46 -0700 |
| commit | 0e6e1d4f440116d604356f5b4aa04765f9663502 (patch) | |
| tree | ef6b59860514df6d5aec60ab13ce96fbb3fbc828 | |
| parent | a1c7d2553cb6fba3d8636355e2a7cb247d047d7c (diff) | |
| download | riscv-isa-manual-0e6e1d4f440116d604356f5b4aa04765f9663502.zip riscv-isa-manual-0e6e1d4f440116d604356f5b4aa04765f9663502.tar.gz riscv-isa-manual-0e6e1d4f440116d604356f5b4aa04765f9663502.tar.bz2 | |
Clarify semantics of sfence.vma with rs1 != 0 (#515)
Based on discussion on the mailing list, the instruction fences accesses not just to one leaf PTE but to any leaf PTE that includes the address (subject to address space constraints specified via rs2).
| -rw-r--r-- | src/supervisor.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index e578ddd..fca210f 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1041,10 +1041,10 @@ SFENCE.VMA depends on {\em rs1} and {\em rs2} as follows: Accesses to {\em global} mappings (see Section~\ref{sec:translation}) are not ordered. \item If {\em rs1}$\neq${\tt x0} and {\em rs2}={\tt x0}, the fence orders - only reads and writes made to the leaf page table entry corresponding + only reads and writes made to leaf page table entries corresponding to the virtual address in {\em rs1}, for all address spaces. \item If {\em rs1}$\neq${\tt x0} and {\em rs2}$\neq${\tt x0}, the fence - orders only reads and writes made to the leaf page table entry + orders only reads and writes made to leaf page table entries corresponding to the virtual address in {\em rs1}, for the address space identified by integer register {\em rs2}. Accesses to global mappings are not ordered. |