aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2021-10-28formatting refinementselisa13-117/+175
2021-10-27change diagram output to png for color to displayelisa33-122/+60
2021-10-27Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa1-0/+2
2021-10-25No valid LR/SC reservation upon resetAndrew Waterman1-0/+2
Closes #758
2021-10-22table and diagram fixes, added some missing c diagramselisa27-85/+156
2021-10-20table and diagram fixeselisa6-15/+46
2021-10-19table fixeselisa2-13/+12
2021-10-18updated pdfelisa1-0/+0
2021-10-18Merge pull request #755 from ved-rivos/ved-patch-4Elisa Sawyer1-387/+276
Chapter 23 : RV32/64G Instruction Set Listings
2021-10-17Fixed the instruction listing tables format.Vedvyas Shanbhogue1-387/+276
2021-10-14table fixeselisa2-206/+186
2021-10-14Merge branch 'convert2adoc' of github.com:riscv/riscv-isa-manual into ↵elisa2-7/+13
convert2adoc
2021-10-14table fixeselisa3-188/+154
2021-10-14Merge pull request #754 from ved-rivos/ved-patch-3Elisa Sawyer2-7/+13
Chapter 24 - Extending
2021-10-13extending.adocVedvyas Shanbhogue2-7/+13
- fixed table formating rv-32-64g.adoc - Added missing cross reference tag - remove extra newline
2021-10-12Merge pull request #753 from riscv/convert2adoc_rvwmoElisa Sawyer1-40/+43
Various RVWMO adoc fixes
2021-10-12RVWMO PPO numbering continuityconvert2adoc_rvwmoDaniel Lustig1-0/+3
2021-10-12Merge pull request #751 from ved-rivos/ved-patch-2Elisa Sawyer8-42/+48
unpriv-chapter-12
2021-10-12Merge pull request #750 from riscv/andrew-fixesElisa Sawyer3-102/+92
Improvements to Intro and RV32I chapters
2021-10-12Various RVWMO adoc fixesDaniel Lustig1-40/+40
2021-10-11f-st-ext.adocVedvyas Shanbhogue8-42/+48
~~~~~~~~~~~~~ 1. removed extra white space ahead of a fcsr instance 2. Removed extra row in Table 7 3. Corrected cross reference to point to Ld/St section chapter 2 4. Fixed wrong wavedrom file included in section 12.7 float-csr.adoc ~~~~~~~~~~~~~~ Add the labels back for fflags and frm sp-load-store.adoc ~~~~~~~~~~~~~~~~~~ 1. Fixed bitfield name that encodes width to denote width and not func3 2. Added bit range to offset. spfloat-classify.adoc ~~~~~~~~~~~~~~~~~~~~~ 1. Fixed attribute to be quoted to avoid repeating spfloat-cn-cmp.adoc ~~~~~~~~~~~~~~~~~~~ 1. Deleted wrongly include FSQRT and replaced with FCVT.int.fmt and FCVT.fmt.int 2. Added missing FSGNJ spfloat-comp.doc ~~~~~~~~~~~~~~~~ 1. Corrected bit field name func3 to rm spfloat-mv.adoc ~~~~~~~~~~~~~~~ 1. Deleted incorrect FMIN-FMAX 2. Added missing FMV.X.W and FMV.W.X spfloat.adoc 1. Corrected the attributes 2. Added missing FSQRT and FMIN-MAX
2021-10-11table fixeselisa6-219/+175
2021-10-10Improvements to Intro and RV32I chaptersAndrew Waterman3-102/+92
Just so I don't lose track of it, here are the issues I noticed that I _didn't_ attempt to address: Sec. 1.5.1: - References to the instruction-length encoding figure show up in the text as "[instlengthcode]" instead of "Figure 1.whatever".  I guess the reason is that the figure isn't captioned? - Likewise references to "Chapter [extensions]" Sec. 1.6: - "Characteristics of traps" table caption is being rendered incorrectly; it's showing up in garbled form in the main text. Sec. 2.1: - Figure 1 is low quality (looks like a screenshot from TeX spec) and needs to be redone. Sec. 2.9: - The HINT table was pretty messed up; I tried to fix it, but you should carefully review it. Sec. 6.2.1: - Encodings for SRAI and SRAIW are incorrect.  Their imm[11:6] field should be 010000, not 100000. Chapter 16: - Looks like the C extension chapter needs a lot of work.  I don't think it makes sense for me to review it yet.
2021-10-07Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa2-71/+53
2021-10-05Fix editing error in mtval/stval definitionAndrew Waterman2-71/+53
Partially introduced by 7f45777bfc3e0a6b327552a286392ccfd5c933a8 and 94ab414c4b470edae8bde4e7759163fe7ddf8ab4 The spec says that the platform will define which exceptions must populate mtval or stval with a nonzero value and which are permitted to zero it. But then later statements seem not to permit the possibility of zeroing the register, which is a contradiction. Resolve in a backwards-compatible manner by permitting zeros unless the platform says otherwise (which was the original intent, anyway). This permits e.g. zeroing mtval on an EBREAK instruction, where mepc provides sufficient information, as was the intent of 94ab414c4b470edae8bde4e7759163fe7ddf8ab4.
2021-10-05adoc formatting and table fixes for intro, a, c, counters, m, rvmo chapterselisa7-489/+477
2021-10-05Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa1-1/+2
2021-10-04Merge pull request #749 from ved-rivos/ved-patch-1Elisa Sawyer2-8/+16
riscv-isa-unpriv.adoc
2021-10-04Clarify order in which PMP CSRs must be implementedAndrew Waterman1-1/+2
2021-10-04editorial fixes chapters 4-8elisa5-75/+73
2021-10-04riscv-isa-unpriv.adocVedvyas Shanbhogue2-8/+16
- fixed missing newline colophon.adoc - fixed first table - missing entries - bolded section header and term "Ratified"
2021-10-04Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa1-3/+3
2021-10-01misc formatting editselisa4-96/+150
2021-10-01Fix permissions of *envcfg CSRsAndrew Waterman1-3/+3
2021-10-01Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa1-5/+4
2021-09-30update to built pdfelisa2-733/+0
2021-09-30Merge pull request #746 from adurbin-rivos/check_manualElisa Sawyer2-7/+13
zihintpause: Annotate notes and correct instruction encoding
2021-09-30zihintpause: Annotate notes and correct instruction encodingAaron Durbin2-7/+13
Chapter 4, Zihintpause, needs the notes annotated in the chapter to align with latex chapter. Additionally, correct PAUSE instruction encoding . Signed-off-by: Aaron Durbin <adurbin@rivosinc.com>
2021-09-30Improve description of FENCE.TSOAndrew Waterman1-5/+4
The description of FENCE.TSO as "optional" was incorrect. It has always been a mandatory instruction (because of the requirement that unused patterns in the fm field be treated as though fm=0).
2021-09-29fixed a few convert problemselisa2-39/+42
2021-09-28some table fixes and additions of missing formattingelisa13-229/+266
2021-09-27Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa2-1/+9
2021-09-21Add example to clarify mip.SEIP behaviorAndrew Waterman1-0/+8
2021-09-21Bump priv version numberAndrew Waterman1-1/+1
2021-09-21minot editselisa4-12/+11
2021-09-21adding some diagram files, adding changes, updating review pdfelisa40-9285/+739
2021-09-17Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa7-26/+47
2021-09-17adding missing image files and placing bibtex file in location where ↵elisa3-0/+513
asciidoctor build will find it
2021-09-15Priv-1.12 spec for public reviewriscv-privileged-20210915-public-reviewAndrew Waterman2-8/+7
2021-09-15JohnH is an editor of the priv specAndrew Waterman1-1/+1
generated by cgit v1.1 at 2024-07-17 22:22:37 +0000