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2021-10-12RVWMO PPO numbering continuityconvert2adoc_rvwmoDaniel Lustig1-0/+3
2021-10-12Various RVWMO adoc fixesDaniel Lustig1-40/+40
2021-10-11table fixeselisa6-219/+175
2021-10-07Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa2-71/+53
2021-10-05Fix editing error in mtval/stval definitionAndrew Waterman2-71/+53
2021-10-05adoc formatting and table fixes for intro, a, c, counters, m, rvmo chapterselisa7-489/+477
2021-10-05Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa1-1/+2
2021-10-04Merge pull request #749 from ved-rivos/ved-patch-1Elisa Sawyer2-8/+16
2021-10-04Clarify order in which PMP CSRs must be implementedAndrew Waterman1-1/+2
2021-10-04editorial fixes chapters 4-8elisa5-75/+73
2021-10-04riscv-isa-unpriv.adocVedvyas Shanbhogue2-8/+16
2021-10-04Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa1-3/+3
2021-10-01misc formatting editselisa4-96/+150
2021-10-01Fix permissions of *envcfg CSRsAndrew Waterman1-3/+3
2021-10-01Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa1-5/+4
2021-09-30update to built pdfelisa2-733/+0
2021-09-30Merge pull request #746 from adurbin-rivos/check_manualElisa Sawyer2-7/+13
2021-09-30zihintpause: Annotate notes and correct instruction encodingAaron Durbin2-7/+13
2021-09-30Improve description of FENCE.TSOAndrew Waterman1-5/+4
2021-09-29fixed a few convert problemselisa2-39/+42
2021-09-28some table fixes and additions of missing formattingelisa13-229/+266
2021-09-27Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa2-1/+9
2021-09-21Add example to clarify mip.SEIP behaviorAndrew Waterman1-0/+8
2021-09-21Bump priv version numberAndrew Waterman1-1/+1
2021-09-21minot editselisa4-12/+11
2021-09-21adding some diagram files, adding changes, updating review pdfelisa40-9285/+739
2021-09-17Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa7-26/+47
2021-09-17adding missing image files and placing bibtex file in location where asciidoc...elisa3-0/+513
2021-09-15Priv-1.12 spec for public reviewriscv-privileged-20210915-public-reviewAndrew Waterman2-8/+7
2021-09-15JohnH is an editor of the priv specAndrew Waterman1-1/+1
2021-09-15RISC-V Foundation -> RISC-V InternationalAndrew Waterman6-12/+12
2021-09-15Freeze the hypervisor extension, version 1.0.0-rc (#739)John Hauser2-4/+7
2021-09-15mip.MSIP and mie.MSIE may be hardwired zeros (#738)John Hauser1-0/+4
2021-09-14Hypervisor extension requires page-based address translation (#737)John Hauser1-1/+2
2021-09-14Fix apparent typo re hpmcounter*h (#735)Scott Johnson1-1/+1
2021-09-14State behavior of uncacheable accesses to cacheable locationsAndrew Waterman1-0/+13
2021-09-14Clarify that WARL fields contain legal values after reset (#734)Andrew Waterman1-0/+1
2021-09-13Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adocelisa2-4/+4
2021-09-11begin adding graphviz fileselisa1-0/+40
2021-09-11adding fonts and theme to use in local buildselisa27-0/+877
2021-09-11Rename STCE to STCD to reverse its polarityAndrew Waterman2-4/+4
2021-09-10adding converted adoc fileselisa38-0/+12831
2021-09-10adding build images and wavedrom source fileselisa45-0/+1034
2021-09-10adding pdf from adoc conversionelisa1-0/+0
2021-09-10Generalize SSIP to support forthcoming interrupt controllers (#726)Andrew Waterman2-23/+4
2021-09-10Speculative implicit reads, v2 (#724)Andrew Waterman3-2/+18
2021-09-09Fix a typo in Figure A.13. (#733)Daniel Lustig1-1/+1
2021-09-08Merge pull request #727 from riscv/mseccfgAndrew Waterman5-2/+393
2021-09-08FIOM may be hardwired when satp is hardwiredAndrew Waterman2-1/+4
2021-09-05Make virtual instruction exceptions more consistent for VU mode (#730)John Hauser1-3/+13
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