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authorDaniel Lustig <dlustig@nvidia.com>2021-10-12 15:08:19 -0400
committerDaniel Lustig <dlustig@nvidia.com>2021-10-12 15:08:19 -0400
commit7c49b5991a52b029d4cbd08aaa5165e981265095 (patch)
treee564cd5302f69521d591dd4adb0119509a38b5e4
parenta85fa837b06b32bae647b98f746f275adc50d6a3 (diff)
downloadriscv-isa-manual-convert2adoc_rvwmo.zip
riscv-isa-manual-convert2adoc_rvwmo.tar.gz
riscv-isa-manual-convert2adoc_rvwmo.tar.bz2
RVWMO PPO numbering continuityconvert2adoc_rvwmo
-rw-r--r--src/rvwmo.adoc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/rvwmo.adoc b/src/rvwmo.adoc
index dad2ae1..1eccd66 100644
--- a/src/rvwmo.adoc
+++ b/src/rvwmo.adoc
@@ -298,6 +298,7 @@ written by different memory operations
generated by an AMO or SC instruction, _b_ is a load, and
_b_ returns a value written by _a_
* Explicit Synchronization
+[start=4]
. There is a FENCE instruction that
orders _a_ before _b_
. _a_ has an acquire
@@ -308,6 +309,7 @@ RCsc annotations
. _a_ is paired with
_b_
* Syntactic Dependencies
+[start=9]
. _b_ has a syntactic address
dependency on _a_
. _b_ has a syntactic data
@@ -315,6 +317,7 @@ dependency on _a_
. _b_ is a store, and
_b_ has a syntactic control dependency on _a_
* Pipeline Dependencies
+[start=12]
. _b_ is a
load, and there exists some store _m_ between
_a_ and _b_ in program order such that