Age | Commit message (Collapse) | Author | Files | Lines | |
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2018-10-25 | The performance counters must respect "c.nop"cnop | Palmer Dabbelt | 1 | -1/+2 | |
The non-compressed "nop" mentions that performance counters are modified by the instruction, but the text of the compressed instruction make it sound like that's not the case. | |||||
2018-10-25 | "c.addi x0, 0" isn't a legal instruction | Palmer Dabbelt | 1 | -2/+1 | |
I was reviewing some QEMU patches recently and noticed an oddity of the current description of the ISA manual: the NOP instruction can also decode as a valid ADDI instruction, but the C.NOP instruction cannot decode as a valid C.ADDI instruction despite the ISA manual saying "C.NOP is encoded as c.addi x0, 0 and so expands to addi x0, x0, 0". This isn't a big deal, because "c.nop" does match what you'd expect the encoding of "c.addi x0, 0", but it is technically incorrect because the instruction "c.addi x0, 0" doesn't exist. This patch fixes the text of "c.nop" to just say it expands to "NOP". Signed-off-by: Palmer Dabbelt <palmer@sifive.com> | |||||
2018-10-18 | WIP on hypervisor | Andrew Waterman | 1 | -224/+592 | |
2018-10-11 | Fix an ambiguity in PLIC spec | Andrew Waterman | 1 | -3/+4 | |
Resolves #239 | |||||
2018-10-09 | Clarify interrupt delegation semantics (#158) | Andrew Waterman | 2 | -3/+11 | |
* Clarify interrupt delegation semantics * Update contributors | |||||
2018-10-09 | Some edits and fixes to memory model sections. (#238) | Prashanth Mundkur | 2 | -11/+11 | |
* Some edits and fixes to memory model sections. * Also fix a typo spotted by @daniellustig. | |||||
2018-10-09 | Added rationale for fused mul-add instructions. | Krste Asanovic | 1 | -8/+20 | |
Closed #224. | |||||
2018-10-09 | Merge branch 'master' of github.com:riscv/riscv-isa-manual | Krste Asanovic | 3 | -1/+29 | |
2018-10-06 | Add PULP cores to marchid.md (#236) | Florian Zaruba | 1 | -6/+8 | |
* Add Ariane to marchid * Add RI5CY to marchid.md | |||||
2018-10-04 | Update marchid.md. (#235) | Christopher Celio | 1 | -0/+1 | |
Add BOOM. | |||||
2018-10-04 | Allocate Spike marchid | Andrew Waterman | 1 | -0/+1 | |
2018-10-04 | Add marchid management document (#234) | Andrew Waterman | 3 | -1/+25 | |
* Fix broken link * Add marchid document | |||||
2018-10-02 | Merge branch 'master' of github.com:riscv/riscv-isa-manual | Krste Asanovic | 1 | -7/+5 | |
2018-09-26 | Custom interrupt priorities are custom | Andrew Waterman | 1 | -4/+4 | |
2018-09-24 | SFENCE behavior is independent of privilege mode | Andrew Waterman | 1 | -3/+1 | |
2018-09-24 | Improving lanuage. | Krste Asanovic | 2 | -7/+7 | |
Closed #215 | |||||
2018-09-24 | Made clear that sepc written on exception or interrupt. | Krste Asanovic | 1 | -4/+4 | |
2018-09-23 | No need for WIRI definition anymore | Andrew Waterman | 1 | -11/+0 | |
2018-09-23 | Unused PMP fields are WARL 0, not WIRI | Andrew Waterman | 2 | -2/+3 | |
2018-09-23 | unused mip fields are wpri instead of wiri | Andrew Waterman | 4 | -12/+13 | |
2018-09-23 | unused misa fields are wlrl, not wiri | Andrew Waterman | 2 | -1/+2 | |
2018-09-23 | Fix an off-by-one error in defining coarse-grained PMPs for NAPOT | Andrew Waterman | 1 | -6/+7 | |
2018-09-23 | hart IDs must be unique | Andrew Waterman | 1 | -1/+1 | |
2018-09-18 | Fix Figure A.2 to make it draw the correct test (#228) | Daniel Lustig | 3 | -15/+17 | |
Luc had provided the correct figure originally, but I must have messed something up in the merge upstream. This restores the correct figure. | |||||
2018-09-10 | Add ECALL from S-mode cause to SCAUSE table | Andrew Waterman | 1 | -2/+3 | |
This won't ever happen if medeleg[9] is hardwired to 0, but medeleg[9] isn't required to be hardwired to 0. | |||||
2018-08-31 | Removed text that implied there was a maximum alignment requirement | Krste Asanovic | 4 | -9/+18 | |
for mtvec, and clarified that different modes can have different mtvec alignment constraints. | |||||
2018-08-30 | Remove text stating C.ADDI4SPN is RV32C/RV64C-only (#223) | Andrew | 1 | -3/+3 | |
The paragraph of text describing C.ADDI4SPN states the instruction is RV32C/RV64C-only, but the opcode map indicates the instruction is available for RV128C too. This change updates the descriptive text, assuming that the opcode map is correct. | |||||
2018-08-29 | Generalized description of counter behavior when not accessible. | Krste Asanovic | 1 | -3/+1 | |
2018-08-29 | Clarify that mtval/mepc are set on interrupts, too | Andrew Waterman | 2 | -5/+5 | |
2018-08-28 | F/D extensions to v2.2 | Andrew Waterman | 3 | -4/+16 | |
2018-08-27 | Move out-of-date vector encoding to V chapter | Andrew Waterman | 3 | -735/+742 | |
2018-08-26 | Clarified that counter-enable fields don't change underlying counter values. | Krste Asanovic | 1 | -0/+6 | |
2018-08-26 | Clarified description of CSR writes to counters per Nikhil's suggestion. | Krste Asanovic | 1 | -8/+7 | |
2018-08-26 | Merge branch 'master' of github.com:riscv/riscv-isa-manual | Krste Asanovic | 2 | -7/+9 | |
2018-08-26 | Updated several "user" references to "unprivileged". | Krste Asanovic | 5 | -12/+13 | |
2018-08-25 | Clarify that FENCE opcode bits aren't required to be 0 | Andrew Waterman | 1 | -7/+5 | |
(They're reserved for future use) | |||||
2018-08-25 | Add semihosting note | Andrew Waterman | 1 | -0/+4 | |
2018-08-12 | Fix typo | Andrew Waterman | 1 | -1/+1 | |
2018-08-12 | Minor tweaks | Andrew Waterman | 2 | -4/+4 | |
2018-08-12 | Improve RV64 32x32->64 text; move to commentary | Andrew Waterman | 1 | -4/+9 | |
2018-08-12 | Tweaks to M extension chapter | Andrew Waterman | 1 | -8/+8 | |
2018-08-12 | Removed redundant text that LR can reserve a different subset on each ↵ | Krste Asanovic | 1 | -3/+1 | |
invocation. | |||||
2018-08-09 | Added specification that xRET instructions may, but are not | Krste Asanovic | 2 | -1/+14 | |
required to, clear LR reservations if A extension present. | |||||
2018-08-09 | Added description of hardware performance counters. | Krste Asanovic | 1 | -0/+21 | |
2018-08-09 | Clarified reservation range and that SC only pairs with immediately ↵ | Krste Asanovic | 1 | -20/+25 | |
preceding LR. | |||||
2018-08-08 | Fix spelling errors | Andrew Waterman | 3 | -6/+6 | |
2018-08-07 | Use \geq instead of >= | Andrew Waterman | 2 | -2/+2 | |
2018-08-07 | Made cleanup pass over floating-point extensions | Krste Asanovic | 4 | -15/+18 | |
2018-08-07 | Broke out actual perf counters into separate chapter. | Krste Asanovic | 4 | -179/+201 | |
2018-08-07 | Clarified A definitions. | Krste Asanovic | 2 | -29/+20 | |