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2018-10-25The performance counters must respect "c.nop"cnopPalmer Dabbelt1-1/+2
2018-10-25"c.addi x0, 0" isn't a legal instructionPalmer Dabbelt1-2/+1
2018-10-18WIP on hypervisorAndrew Waterman1-224/+592
2018-10-11Fix an ambiguity in PLIC specAndrew Waterman1-3/+4
2018-10-09Clarify interrupt delegation semantics (#158)Andrew Waterman2-3/+11
2018-10-09Some edits and fixes to memory model sections. (#238)Prashanth Mundkur2-11/+11
2018-10-09Added rationale for fused mul-add instructions.Krste Asanovic1-8/+20
2018-10-09Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic3-1/+29
2018-10-06Add PULP cores to marchid.md (#236)Florian Zaruba1-6/+8
2018-10-04Update marchid.md. (#235)Christopher Celio1-0/+1
2018-10-04Allocate Spike marchidAndrew Waterman1-0/+1
2018-10-04Add marchid management document (#234)Andrew Waterman3-1/+25
2018-10-02Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-7/+5
2018-09-26Custom interrupt priorities are customAndrew Waterman1-4/+4
2018-09-24SFENCE behavior is independent of privilege modeAndrew Waterman1-3/+1
2018-09-24Improving lanuage.Krste Asanovic2-7/+7
2018-09-24Made clear that sepc written on exception or interrupt.Krste Asanovic1-4/+4
2018-09-23No need for WIRI definition anymoreAndrew Waterman1-11/+0
2018-09-23Unused PMP fields are WARL 0, not WIRIAndrew Waterman2-2/+3
2018-09-23unused mip fields are wpri instead of wiriAndrew Waterman4-12/+13
2018-09-23unused misa fields are wlrl, not wiriAndrew Waterman2-1/+2
2018-09-23Fix an off-by-one error in defining coarse-grained PMPs for NAPOTAndrew Waterman1-6/+7
2018-09-23hart IDs must be uniqueAndrew Waterman1-1/+1
2018-09-18Fix Figure A.2 to make it draw the correct test (#228)Daniel Lustig3-15/+17
2018-09-10Add ECALL from S-mode cause to SCAUSE tableAndrew Waterman1-2/+3
2018-08-31Removed text that implied there was a maximum alignment requirementKrste Asanovic4-9/+18
2018-08-30Remove text stating C.ADDI4SPN is RV32C/RV64C-only (#223)Andrew1-3/+3
2018-08-29Generalized description of counter behavior when not accessible.Krste Asanovic1-3/+1
2018-08-29Clarify that mtval/mepc are set on interrupts, tooAndrew Waterman2-5/+5
2018-08-28F/D extensions to v2.2Andrew Waterman3-4/+16
2018-08-27Move out-of-date vector encoding to V chapterAndrew Waterman3-735/+742
2018-08-26Clarified that counter-enable fields don't change underlying counter values.Krste Asanovic1-0/+6
2018-08-26Clarified description of CSR writes to counters per Nikhil's suggestion.Krste Asanovic1-8/+7
2018-08-26Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic2-7/+9
2018-08-26Updated several "user" references to "unprivileged".Krste Asanovic5-12/+13
2018-08-25Clarify that FENCE opcode bits aren't required to be 0Andrew Waterman1-7/+5
2018-08-25Add semihosting noteAndrew Waterman1-0/+4
2018-08-12Fix typoAndrew Waterman1-1/+1
2018-08-12Minor tweaksAndrew Waterman2-4/+4
2018-08-12Improve RV64 32x32->64 text; move to commentaryAndrew Waterman1-4/+9
2018-08-12Tweaks to M extension chapterAndrew Waterman1-8/+8
2018-08-12Removed redundant text that LR can reserve a different subset on each invocat...Krste Asanovic1-3/+1
2018-08-09Added specification that xRET instructions may, but are notKrste Asanovic2-1/+14
2018-08-09Added description of hardware performance counters.Krste Asanovic1-0/+21
2018-08-09Clarified reservation range and that SC only pairs with immediately preceding...Krste Asanovic1-20/+25
2018-08-08Fix spelling errorsAndrew Waterman3-6/+6
2018-08-07Use \geq instead of >=Andrew Waterman2-2/+2
2018-08-07Made cleanup pass over floating-point extensionsKrste Asanovic4-15/+18
2018-08-07Broke out actual perf counters into separate chapter.Krste Asanovic4-179/+201
2018-08-07Clarified A definitions.Krste Asanovic2-29/+20
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