Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2017-11-29 | Update preface.texaswaterman-patch-1 | Andrew Waterman | 1 | -0/+1 | |
2017-11-27 | Add R-type format to priv-instr-table | Andrew Waterman | 1 | -0/+10 | |
Closes #115 | |||||
2017-11-12 | Clarify WLRL semantics | Andrew Waterman | 1 | -1/+1 | |
2017-11-12 | Mark useless PMP NAPOT case as reserved | Andrew Waterman | 1 | -0/+1 | |
2017-11-09 | Make MPP/SPP WARL fields | Andrew Waterman | 2 | -3/+7 | |
2017-11-09 | State that writable-but-not-readable PMPs are reserved | Andrew Waterman | 1 | -1/+2 | |
2017-11-09 | Specify meaning of R/W/X bits in PMP | Andrew Waterman | 1 | -0/+8 | |
2017-11-09 | Specify meaning of R/W/X bits in PTE | Andrew Waterman | 1 | -0/+13 | |
2017-11-09 | Add hypervisor draft proposal | Andrew Waterman | 3 | -5/+1097 | |
2017-11-09 | fix typos | Andrew Waterman | 4 | -8/+8 | |
2017-11-01 | Document the 'DYN' mnemonic for dynamic rounding mode (#111) | Alex Bradbury | 1 | -1/+1 | |
This mnemonic has been adopted by the GNU assembler in addition to the RNE/RTZ/RDN/RUP/RMM mnemonics currently described here. | |||||
2017-10-30 | tweak wording | Andrew Waterman | 1 | -1/+1 | |
2017-10-21 | Update contributors | Andrew Waterman | 1 | -1/+1 | |
2017-10-20 | Specify that user-ISA LR/SC constraints apply to main memory | Andrew Waterman | 1 | -0/+8 | |
2017-10-20 | Remove privileged architecture detail from user spec | Andrew Waterman | 1 | -3/+11 | |
2017-10-20 | Put the onus on software to align pc/epc when clearing misa.C | Andrew Waterman | 1 | -0/+3 | |
2017-10-11 | Fix outdated commentary on mcounteren | Andrew Waterman | 1 | -2/+2 | |
2017-09-26 | Generalize an Sv32 sentence to apply to SvXX | Andrew Waterman | 1 | -1/+1 | |
2017-09-20 | Remove potential ambiguity in JALR commentary | Andrew Waterman | 1 | -2/+2 | |
2017-09-20 | Clarify mtval; allow platform to specify when it's written | Andrew Waterman | 2 | -15/+27 | |
2017-09-20 | Describe MSIE/SSIE/USIE | Andrew Waterman | 1 | -0/+4 | |
Closes #105 | |||||
2017-09-13 | Sv48 must imply Sv39 | Andrew Waterman | 1 | -2/+2 | |
2017-09-10 | Merge pull request #102 from respasa/master | Krste Asanovic | 1 | -0/+4 | |
Update v.tex | |||||
2017-08-31 | Update v.tex | respasa | 1 | -0/+4 | |
2017-08-17 | Always order interrupt priority by privilege mode | Andrew Waterman | 2 | -5/+5 | |
https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/_SECLWl8qWk | |||||
2017-08-15 | Load address misaligned exceptions *can* occur in S-mode | Andrew Waterman | 1 | -8/+9 | |
because of the load-reserved instruction. | |||||
2017-08-15 | Clarify interrupt priority order | Andrew Waterman | 2 | -13/+11 | |
2017-08-15 | Fix typo in mideleg caption (#98) | stkaplan | 1 | -1/+1 | |
2017-08-05 | README.md: List the contained volumes (#97) | neuschaefer | 1 | -1/+4 | |
2017-07-30 | clarify that more-privileged interrupts are of higher priority | Andrew Waterman | 1 | -4/+6 | |
2017-07-27 | Make RV32 SRAI description match RV64 | Andrew Waterman | 1 | -1/+1 | |
This change is cosmetic, but seems like an improvement. | |||||
2017-07-26 | Fix typo in stvec figure | Andrew Waterman | 1 | -1/+1 | |
Closes #95 | |||||
2017-07-22 | Explained why vl setting rule changed. | Krste Asanovic | 1 | -0/+2 | |
2017-07-22 | Merge branch 'master' of github.com:riscv/riscv-isa-manual | Krste Asanovic | 3 | -4/+12 | |
2017-07-21 | Fix description of LR/SC for data size | Andrew Waterman | 2 | -4/+5 | |
LR.D/SC.W and LR.W/SC.D aren't guaranteed to succeed. | |||||
2017-07-20 | Add note about C.MV | Andrew Waterman | 1 | -0/+7 | |
2017-07-19 | Changed vector-length-setting formula to guarantee monotonically decreasing ↵ | Krste Asanovic | 1 | -1/+1 | |
vector lengths. | |||||
2017-07-11 | First sketch of vector extension sent to V Task Group. | Krste Asanovic | 2 | -620/+724 | |
2017-07-06 | Temp checkpoint to send to Roger. | Krste Asanovic | 2 | -252/+631 | |
2017-07-01 | Clarify Float Compare description | ds2horner | 2 | -6/+8 | |
Modeled after SLT description: Make register compare order explicit (rs1 to rs2) Make Boolean result explicit (1 written if true, zero otherwise). | |||||
2017-06-26 | Fix typo in PMP address CSR bit field diagram | Richard Xia | 1 | -1/+1 | |
It looks like there was a copy and paste bug between the RV32 and RV64 version of the `pmpaddr` diagram. This changes the diagram to correctly display the bit widths of the fields in RV64. | |||||
2017-06-26 | Change remaining SCALL/SBREAK reference to ECALL/EBREAK | sal | 1 | -1/+1 | |
Signed-off-by: ds2horner <ds2horner@gmail.com> | |||||
2017-06-24 | Fix typo | Andrew Waterman | 1 | -1/+1 | |
2017-06-20 | fix typo | Andrew Waterman | 1 | -2/+2 | |
2017-06-19 | Add MULHSU commentary | Andrew Waterman | 1 | -0/+6 | |
2017-06-15 | Correct CALL macro | Andrew Waterman | 1 | -2/+2 | |
2017-06-14 | Remove FSFLAGSI, FSRMI pseudoinstructions | Andrew Waterman | 2 | -7/+1 | |
They have never implemented and are too uncommon to justify pseudoinstructions instead of using CSRWI/CSRRWI directly. | |||||
2017-06-12 | Use the official DOI website for linking to DOIs | Paul Wise | 1 | -1/+1 | |
Redirects to the same place as the ACM website but this also means it can use https. | |||||
2017-06-12 | Update link to 'MIPS32 Architecture for Programmers' document | Paul Wise | 1 | -1/+1 | |
The existing link redirects to a generic MIPS page, while the new link lists downloads for the document. | |||||
2017-06-12 | Use https for link to riscv.org | Paul Wise | 1 | -1/+1 | |
Prevents MITM attacks on RISC-V Foundation website visitors. |