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AgeCommit message (Expand)AuthorFilesLines
2017-11-29Update preface.texaswaterman-patch-1Andrew Waterman1-0/+1
2017-11-27Add R-type format to priv-instr-tableAndrew Waterman1-0/+10
2017-11-12Clarify WLRL semanticsAndrew Waterman1-1/+1
2017-11-12Mark useless PMP NAPOT case as reservedAndrew Waterman1-0/+1
2017-11-09Make MPP/SPP WARL fieldsAndrew Waterman2-3/+7
2017-11-09State that writable-but-not-readable PMPs are reservedAndrew Waterman1-1/+2
2017-11-09Specify meaning of R/W/X bits in PMPAndrew Waterman1-0/+8
2017-11-09Specify meaning of R/W/X bits in PTEAndrew Waterman1-0/+13
2017-11-09Add hypervisor draft proposalAndrew Waterman3-5/+1097
2017-11-09fix typosAndrew Waterman4-8/+8
2017-11-01Document the 'DYN' mnemonic for dynamic rounding mode (#111)Alex Bradbury1-1/+1
2017-10-30tweak wordingAndrew Waterman1-1/+1
2017-10-21Update contributorsAndrew Waterman1-1/+1
2017-10-20Specify that user-ISA LR/SC constraints apply to main memoryAndrew Waterman1-0/+8
2017-10-20Remove privileged architecture detail from user specAndrew Waterman1-3/+11
2017-10-20Put the onus on software to align pc/epc when clearing misa.CAndrew Waterman1-0/+3
2017-10-11Fix outdated commentary on mcounterenAndrew Waterman1-2/+2
2017-09-26Generalize an Sv32 sentence to apply to SvXXAndrew Waterman1-1/+1
2017-09-20Remove potential ambiguity in JALR commentaryAndrew Waterman1-2/+2
2017-09-20Clarify mtval; allow platform to specify when it's writtenAndrew Waterman2-15/+27
2017-09-20Describe MSIE/SSIE/USIEAndrew Waterman1-0/+4
2017-09-13Sv48 must imply Sv39Andrew Waterman1-2/+2
2017-09-10Merge pull request #102 from respasa/masterKrste Asanovic1-0/+4
2017-08-31Update v.texrespasa1-0/+4
2017-08-17Always order interrupt priority by privilege modeAndrew Waterman2-5/+5
2017-08-15Load address misaligned exceptions *can* occur in S-modeAndrew Waterman1-8/+9
2017-08-15Clarify interrupt priority orderAndrew Waterman2-13/+11
2017-08-15Fix typo in mideleg caption (#98)stkaplan1-1/+1
2017-08-05README.md: List the contained volumes (#97)neuschaefer1-1/+4
2017-07-30clarify that more-privileged interrupts are of higher priorityAndrew Waterman1-4/+6
2017-07-27Make RV32 SRAI description match RV64Andrew Waterman1-1/+1
2017-07-26Fix typo in stvec figureAndrew Waterman1-1/+1
2017-07-22Explained why vl setting rule changed.Krste Asanovic1-0/+2
2017-07-22Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic3-4/+12
2017-07-21Fix description of LR/SC for data sizeAndrew Waterman2-4/+5
2017-07-20Add note about C.MVAndrew Waterman1-0/+7
2017-07-19Changed vector-length-setting formula to guarantee monotonically decreasing v...Krste Asanovic1-1/+1
2017-07-11First sketch of vector extension sent to V Task Group.Krste Asanovic2-620/+724
2017-07-06Temp checkpoint to send to Roger.Krste Asanovic2-252/+631
2017-07-01Clarify Float Compare descriptionds2horner2-6/+8
2017-06-26Fix typo in PMP address CSR bit field diagramRichard Xia1-1/+1
2017-06-26Change remaining SCALL/SBREAK reference to ECALL/EBREAKsal1-1/+1
2017-06-24Fix typoAndrew Waterman1-1/+1
2017-06-20fix typoAndrew Waterman1-2/+2
2017-06-19Add MULHSU commentaryAndrew Waterman1-0/+6
2017-06-15Correct CALL macroAndrew Waterman1-2/+2
2017-06-14Remove FSFLAGSI, FSRMI pseudoinstructionsAndrew Waterman2-7/+1
2017-06-12Use the official DOI website for linking to DOIsPaul Wise1-1/+1
2017-06-12Update link to 'MIPS32 Architecture for Programmers' documentPaul Wise1-1/+1
2017-06-12Use https for link to riscv.orgPaul Wise1-1/+1
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