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| author | Andrew Waterman <aswaterman@gmail.com> | 2017-11-29 13:05:31 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-11-29 13:05:31 -0800 |
| commit | 6a61277c608af74cfd64d524b4643d1f4349b3bb (patch) | |
| tree | 35e1018394aa0c27c02a35d0e04f9ff22ef1d734 | |
| parent | 9f22e9a9d7b3e3d9649fb0a9d1d0b48821037222 (diff) | |
| download | riscv-isa-manual-aswaterman-patch-1.zip riscv-isa-manual-aswaterman-patch-1.tar.gz riscv-isa-manual-aswaterman-patch-1.tar.bz2 | |
Update preface.texaswaterman-patch-1
| -rw-r--r-- | src/preface.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/preface.tex b/src/preface.tex index f223c92..fe47387 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -10,6 +10,7 @@ versions of the RISC-V ISA modules: Base & Version & Frozen? \\ \hline RV32I & 2.0 & Y \\ + asdfasdfsasdfa RV32E & 1.9 & N \\ RV64I & 2.0 & Y \\ RV128I & 1.7 & N \\ |