diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/hypervisor.adoc | 12 | ||||
-rw-r--r-- | src/images/bytefield/hedelegreg.edn | 6 | ||||
-rw-r--r-- | src/images/bytefield/medeleg.adoc | 6 | ||||
-rw-r--r-- | src/machine.adoc | 9 | ||||
-rw-r--r-- | src/priv-csrs.adoc | 20 | ||||
-rw-r--r-- | src/priv-preface.adoc | 1 |
6 files changed, 37 insertions, 17 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index cb900b0..00b1fcb 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -272,9 +272,11 @@ same endianness as HS-mode. ==== Hypervisor Trap Delegation Registers (`hedeleg` and `hideleg`) -Registers `hedeleg` and `hideleg` are HSXLEN-bit read/write registers, -formatted as shown in <<hedelegreg>> and -<<hidelegreg>> respectively. By default, all traps at +Register `hedeleg` is a 64-bit read/write register, formatted as shown in +<<hedelegreg>>. +Register `hideleg` is an HSXLEN-bit read/write register, formatted as shown in +<<hidelegreg>>. +By default, all traps at any privilege level are handled in M-mode, though M-mode usually uses the `medeleg` and `mideleg` CSRs to delegate some traps to HS-mode. The `hedeleg` and `hideleg` CSRs allow these traps to be further delegated @@ -303,6 +305,10 @@ Requiring that certain bits of `hedeleg` be writable reduces some of the burden on a hypervisor to handle variations of implementation. ==== +When XLEN=32, `hedelegh` is a 32-bit read/write register +that aliases bits 63:32 of `hedeleg`. +Register `hedelegh` does not exist when XLEN=64. + An interrupt that has been delegated to HS-mode (using `mideleg`) is further delegated to VS-mode if the corresponding `hideleg` bit is set. Among bits 15:0 of `hideleg`, bits 10, 6, and 2 (corresponding to the diff --git a/src/images/bytefield/hedelegreg.edn b/src/images/bytefield/hedelegreg.edn index 8348f22..48c452c 100644 --- a/src/images/bytefield/hedelegreg.edn +++ b/src/images/bytefield/hedelegreg.edn @@ -7,11 +7,11 @@ (def right-margin 30) (def boxes-per-row 32) -(draw-box "HSXLEN-1" {:span 16 :text-anchor "start" :borders{}}) +(draw-box "63" {:span 16 :text-anchor "start" :borders{}}) (draw-box "0" {:span 16 :text-anchor "end" :borders{}}) (draw-box "Synchronous Exceptions" {:span 18 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}}) (draw-box (text "(WARL)" { :font-weight "bold" :font-size 24}) {:span 14 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}}) -(draw-box "HSXLEN" {:span 32 :borders {}}) -----
\ No newline at end of file +(draw-box "64" {:span 32 :borders {}}) +---- diff --git a/src/images/bytefield/medeleg.adoc b/src/images/bytefield/medeleg.adoc index 2abd97b..a63156d 100644 --- a/src/images/bytefield/medeleg.adoc +++ b/src/images/bytefield/medeleg.adoc @@ -7,11 +7,11 @@ (def right-margin 100) (def boxes-per-row 32) -(draw-box "MXLEN-1" {:span 16 :text-anchor "start" :borders {}}) +(draw-box "63" {:span 16 :text-anchor "start" :borders {}}) (draw-box "0" {:span 16 :text-anchor "end" :borders {}}) (draw-box "Synchronous Exceptions" {:font-size 18 :span 18 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}}) (draw-box (text "(WARL)" {:font-weight "bold"}) {:font-size 18 :span 14 :text-anchor "start" :borders {:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}}) -(draw-box "MXLEN" {:font-size 24 :span 32 :borders {}}) -----
\ No newline at end of file +(draw-box "64" {:font-size 24 :span 32 :borders {}}) +---- diff --git a/src/machine.adoc b/src/machine.adoc index 2160257..c98b128 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -1134,8 +1134,9 @@ appropriate level with the MRET instruction implementations can provide individual read/write bits within `medeleg` and `mideleg` to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level. The machine exception -delegation register (`medeleg`) and machine interrupt delegation -register (`mideleg`) are MXLEN-bit read/write registers. +delegation register (`medeleg`) is a 64-bit read/write register. +The machine interrupt delegation register (`mideleg`) is an MXLEN-bit +read/write register. In systems with S-mode, the `medeleg` and `mideleg` registers must exist, and setting a bit in `medeleg` or `mideleg` will delegate the @@ -1203,6 +1204,10 @@ bit position equal to the value returned in the `mcause` register (i.e., setting bit 8 allows user-mode environment calls to be delegated to a lower-privilege trap handler). +When XLEN=32, `medelegh` is a 32-bit read/write register +that aliases bits 63:32 of `medeleg`. +Register `medelegh` does not exist when XLEN=64. + .Machine Interrupt Delegation Register `mideleg`. include::images/bytefield/mideleg.adoc[] diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc index d603b44..7a0773b 100644 --- a/src/priv-csrs.adoc +++ b/src/priv-csrs.adoc @@ -438,25 +438,29 @@ Supervisor interrupt pending. `0x603` + `0x604` + `0x606` + -`0x607` +`0x607` + +`0x612` |HRW + HRW + HRW + HRW + HRW + +HRW + HRW |`hstatus` + `hedeleg` + `hideleg` + `hie` + `hcounteren` + -`hgeie` +`hgeie` + +`hedelegh` |Hypervisor status register. + Hypervisor exception delegation register. + Hypervisor interrupt delegation register. + Hypervisor interrupt-enable register. + Hypervisor counter enable. + -Hypervisor guest external interrupt-enable register. +Hypervisor guest external interrupt-enable register. + +Upper 32 bits of `hedeleg`, RV32 only. 4+^|Hypervisor Trap Handling @@ -590,7 +594,8 @@ Pointer to configuration data structure. `0x304` + `0x305` + `0x306` + -`0x310` +`0x310` + +`0x312` |MRW + MRW + MRW + @@ -598,6 +603,7 @@ MRW + MRW + MRW + MRW + +MRW + MRW |`mstatus` + `misa` + @@ -606,7 +612,8 @@ MRW `mie` + `mtvec` + `mcounteren` + -`mstatush` +`mstatush` + +`medelegh` |Machine status register. + ISA and extensions + Machine exception delegation register. + @@ -614,7 +621,8 @@ Machine interrupt delegation register. + Machine interrupt-enable register. + Machine trap-handler base address. + Machine counter enable. + -Additional machine status register, RV32 only. +Additional machine status register, RV32 only. + +Upper 32 bits of `medeleg`, RV32 only. 4+^|Machine Trap Handling diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index e0177ee..a024490 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -36,6 +36,7 @@ version 1.12: * Defined the `misa`.V field to reflect that the V extension has been implemented. +* Defined the RV32-only `medelegh` and `hedelegh` CSRs. * Specified synchronization requirements when changing the PBMTE fields in `menvcfg` and `henvcfg`. * Clarified semantics of explicit accesses to CSRs wider than XLEN bits. |