diff options
Diffstat (limited to 'src/images')
196 files changed, 1716 insertions, 1874 deletions
diff --git a/src/images/bytefield/hypv-miereg-standard.edn b/src/images/bytefield/hypv-miereg-standard.edn index 154983d..e2b60ab 100644 --- a/src/images/bytefield/hypv-miereg-standard.edn +++ b/src/images/bytefield/hypv-miereg-standard.edn @@ -8,9 +8,9 @@ (def boxes-per-row 32) (draw-box "15" {:borders {}}) -(draw-box nil {:span 2 :borders {}}) -(draw-box "13" {:borders {}}) -(draw-box "12" {:span 3 :borders {}}) +(draw-box "14" {:borders {}}) +(draw-box "13" {:span 3 :borders {}}) +(draw-box "12" {:span 2 :borders {}}) (draw-box "11" {:span 2 :borders {}}) (draw-box "10" {:span 3 :borders {}}) (draw-box "9" {:span 2 :borders {}}) @@ -24,8 +24,9 @@ (draw-box "1" {:span 2 :borders {}}) (draw-box "0" {:span 2 :borders {}}) -(draw-box "0" {:span 4}) -(draw-box "SGEIE" {:span 3}) +(draw-box "0" {:span 2}) +(draw-box "LCOFIE" {:span 3}) +(draw-box "SGEIE" {:span 2}) (draw-box "MEIE" {:span 2}) (draw-box "VSEIE" {:span 3}) (draw-box "SEIE" {:span 2}) @@ -39,8 +40,9 @@ (draw-box "SSIE" {:span 2}) (draw-box "0" {:span 2}) -(draw-box "3" {:span 4 :borders {}}) -(draw-box "1" {:span 3:borders {}}) +(draw-box "2" {:span 2 :borders {}}) +(draw-box "1" {:span 3 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 3 :borders {}}) (draw-box "1" {:span 2 :borders {}}) diff --git a/src/images/bytefield/hypv-mipreg-standard.edn b/src/images/bytefield/hypv-mipreg-standard.edn index c75ec02..f41a1ba 100644 --- a/src/images/bytefield/hypv-mipreg-standard.edn +++ b/src/images/bytefield/hypv-mipreg-standard.edn @@ -8,9 +8,9 @@ (def boxes-per-row 32) (draw-box "15" {:borders {}}) -(draw-box nil {:span 2 :borders {}}) -(draw-box "13" {:borders {}}) -(draw-box "12" {:span 3 :borders {}}) +(draw-box "14" {:borders {}}) +(draw-box "13" {:span 3 :borders {}}) +(draw-box "12" {:span 2 :borders {}}) (draw-box "11" {:span 2 :borders {}}) (draw-box "10" {:span 3 :borders {}}) (draw-box "9" {:span 2 :borders {}}) @@ -24,8 +24,9 @@ (draw-box "1" {:span 2 :borders {}}) (draw-box "0" {:span 2 :borders {}}) -(draw-box "0" {:span 4}) -(draw-box "SGEIP" {:span 3}) +(draw-box "0" {:span 2}) +(draw-box "LCOFIP" {:span 3}) +(draw-box "SGEIP" {:span 2}) (draw-box "MEIP" {:span 2}) (draw-box "VSEIP" {:span 3}) (draw-box "SEIP" {:span 2}) @@ -39,8 +40,9 @@ (draw-box "SSIP" {:span 2}) (draw-box "0" {:span 2}) -(draw-box "3" {:span 4 :borders {}}) -(draw-box "1" {:span 3:borders {}}) +(draw-box "2" {:span 2 :borders {}}) +(draw-box "1" {:span 3 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:span 3 :borders {}}) (draw-box "1" {:span 2 :borders {}}) diff --git a/src/images/bytefield/rvc-instr-quad1.adoc b/src/images/bytefield/rvc-instr-quad1.adoc index e0f6073..3aebd40 100644 --- a/src/images/bytefield/rvc-instr-quad1.adoc +++ b/src/images/bytefield/rvc-instr-quad1.adoc @@ -14,7 +14,7 @@ (draw-box "0" {:span 5}) (draw-box "imm[4:0]" {:span 5}) (draw-box "01" {:span 2}) -(draw-box (text "C.NOP" :math [:sub "(HINT, imm=0)"]) {:span 3 :text-anchor "start" :borders {}}) +(draw-box (text "C.NOP" :math [:sub "(HINT, imm≠0)"]) {:span 3 :text-anchor "start" :borders {}}) (draw-box "000" {:span 3}) (draw-box "imm[5]") {:span 1} diff --git a/src/images/wavedrom/atomic-mem.adoc b/src/images/wavedrom/atomic-mem.adoc deleted file mode 100644 index ef66028..0000000 --- a/src/images/wavedrom/atomic-mem.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 9.4 Atomic Memory Operations - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7','AMO','AMO','AMO','AMO','AMO','AMO','AMO']}, - {bits: 5, name: 'rd', type: 2, attr: ['5','dest','dest','dest','dest','dest','dest','dest']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','width','width','width','width','width','width','width']}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','addr','addr','addr','addr','addr','addr','addr']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','src','src','src','src','src','src','src']}, - {bits: 1, name: 'rl', type: 8, attr: ['1']}, - {bits: 1, name: 'aq', type: 8, attr: ['1']}, - {bits: 6, name: 'funct5', type: 8, attr: ['5','AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D','AMOMIN[U].W/D']}, -], config: {bits: 32}} -.... diff --git a/src/images/wavedrom/atomic-mem.edn b/src/images/wavedrom/atomic-mem.edn new file mode 100644 index 0000000..1e95eb4 --- /dev/null +++ b/src/images/wavedrom/atomic-mem.edn @@ -0,0 +1,15 @@ +//## 9.4 Atomic Memory Operations + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','AMO','AMO','AMO','AMO','AMO','AMO','AMO']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest','dest','dest','dest']}, + {bits: 3, name: 'funct3', attr: ['3','width','width','width','width','width','width','width']}, + {bits: 5, name: 'rs1', attr: ['5','addr','addr','addr','addr','addr','addr','addr']}, + {bits: 5, name: 'rs2', attr: ['5','src','src','src','src','src','src','src']}, + {bits: 1, name: 'rl', attr: ['1']}, + {bits: 1, name: 'aq', attr: ['1']}, + {bits: 6, name: 'funct5', attr: ['5','AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D','AMOMIN[U].W/D']}, +], config: {bits: 32}} +.... diff --git a/src/images/wavedrom/b-immediate.edn b/src/images/wavedrom/b-immediate.edn new file mode 100644 index 0000000..fcf9aad --- /dev/null +++ b/src/images/wavedrom/b-immediate.edn @@ -0,0 +1,12 @@ +//#### B-immediate + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: '0'}, + {bits: 4, name: 'inst[11:8]'}, + {bits: 6, name: 'inst[30:25]'}, + {bits: 1, name: '[7]'}, + {bits: 20, name: '— inst[31] —'}, +], config:{fontsize: 12, label:{right: 'B-immediate'}}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/c-andi.adoc b/src/images/wavedrom/c-andi.adoc deleted file mode 100644 index 5eca644..0000000 --- a/src/images/wavedrom/c-andi.adoc +++ /dev/null @@ -1,13 +0,0 @@ -//c-andi.adoc - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 5, attr: ['2','C1'],}, - {bits: 5, name: 'imm[4:0]', type: 5, attr: ['5','imm[4:0]']}, - {bits: 3, name: 'rd′/rs1′', type: 5, attr: ['3','dest'],}, - {bits: 2, name: 'funct2', type: 5, attr: ['2','C.ANDI'],}, - {bits: 1, name: 'imm[5]', type: 1, attr: ['1','imm[5]'],}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.ANDI'],}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/c-andi.edn b/src/images/wavedrom/c-andi.edn new file mode 100644 index 0000000..3ea3206 --- /dev/null +++ b/src/images/wavedrom/c-andi.edn @@ -0,0 +1,13 @@ +//c-andi.adoc + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C1'],}, + {bits: 5, name: 'imm[4:0]', attr: ['5','imm[4:0]']}, + {bits: 3, name: 'rd′/rs1′', attr: ['3','dest'],}, + {bits: 2, name: 'funct2', attr: ['2','C.ANDI'],}, + {bits: 1, name: 'imm[5]', attr: ['1','imm[5]'],}, + {bits: 3, name: 'funct3', attr: ['3','C.ANDI'],}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/c-breakpoint-instr.adoc b/src/images/wavedrom/c-breakpoint-instr.adoc deleted file mode 100644 index 99ae2d5..0000000 --- a/src/images/wavedrom/c-breakpoint-instr.adoc +++ /dev/null @@ -1,11 +0,0 @@ -// - -[wavedrom, ,svg] - -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C2'],}, - {bits: 10, name: '0', type: 4, attr: ['10','0'],}, - {bits: 4, name: 'funct4', type: 8, attr: ['4','C.EBREAK'],}, -], config: {bits: 16}} -....
\ No newline at end of file diff --git a/src/images/wavedrom/c-breakpoint-instr.edn b/src/images/wavedrom/c-breakpoint-instr.edn new file mode 100644 index 0000000..6ae1890 --- /dev/null +++ b/src/images/wavedrom/c-breakpoint-instr.edn @@ -0,0 +1,11 @@ +// + +[wavedrom, ,svg] + +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C2'],}, + {bits: 10, name: '0', attr: ['10','0'],}, + {bits: 4, name: 'funct4', attr: ['4','C.EBREAK'],}, +], config: {bits: 16}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/c-cb-format-ls.adoc b/src/images/wavedrom/c-cb-format-ls.adoc deleted file mode 100644 index daf2248..0000000 --- a/src/images/wavedrom/c-cb-format-ls.adoc +++ /dev/null @@ -1,13 +0,0 @@ -//c-cb-format-ls - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C1', 'C1']}, - {bits: 5, name: 'imm', type: 3, attr: ['5','offset[7:6|2:1|5]', 'offset[7:6|2:1|5]']}, - {bits: 3, name: 'rs1′', type: 4, attr: ['3','src', 'src']}, - {bits: 3, name: 'imm', type: 3, attr: ['3','offset[8|4:3]', 'offset[8|4:3]'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','C.BEQZ', 'C.BNEZ'],}, -], config: {bits: 16}} -.... - diff --git a/src/images/wavedrom/c-cb-format-ls.edn b/src/images/wavedrom/c-cb-format-ls.edn new file mode 100644 index 0000000..5c90133 --- /dev/null +++ b/src/images/wavedrom/c-cb-format-ls.edn @@ -0,0 +1,13 @@ +//c-cb-format-ls + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C1', 'C1']}, + {bits: 5, name: 'imm', attr: ['5','offset[7:6|2:1|5]', 'offset[7:6|2:1|5]']}, + {bits: 3, name: 'rs1′', attr: ['3','src', 'src']}, + {bits: 3, name: 'imm', attr: ['3','offset[8|4:3]', 'offset[8|4:3]'],}, + {bits: 3, name: 'funct3', attr: ['3','C.BEQZ', 'C.BNEZ'],}, +], config: {bits: 16}} +.... + diff --git a/src/images/wavedrom/c-ci.adoc b/src/images/wavedrom/c-ci.adoc deleted file mode 100644 index 7dae51e..0000000 --- a/src/images/wavedrom/c-ci.adoc +++ /dev/null @@ -1,13 +0,0 @@ -// - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2', 'C2']}, - {bits: 5, name: 'shamt[4:0]', type: 1, attr: ['5', 'shamt[4:0]']}, - {bits: 5, name: 'rd/rs1', type: 5, attr: ['5', 'dest != 0']}, - {bits: 1, name: 'shamt[5]', type: 5, attr: ['1', 'shamt[5]']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3', 'C.SLLI']}, -]} -.... - diff --git a/src/images/wavedrom/c-ci.edn b/src/images/wavedrom/c-ci.edn new file mode 100644 index 0000000..aacf2be --- /dev/null +++ b/src/images/wavedrom/c-ci.edn @@ -0,0 +1,13 @@ +// + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2', 'C2']}, + {bits: 5, name: 'shamt[4:0]', attr: ['5', 'shamt[4:0]']}, + {bits: 5, name: 'rd/rs1', attr: ['5', 'dest != 0']}, + {bits: 1, name: 'shamt[5]', attr: ['1', 'shamt[5]']}, + {bits: 3, name: 'funct3', attr: ['3', 'C.SLLI']}, +]} +.... + diff --git a/src/images/wavedrom/c-ciw.adoc b/src/images/wavedrom/c-ciw.adoc deleted file mode 100644 index 111b272..0000000 --- a/src/images/wavedrom/c-ciw.adoc +++ /dev/null @@ -1,12 +0,0 @@ -//c-ciw.adoc - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2','C0'],}, - {bits: 3, name: 'rd′', type: 5, attr: ['3','dest'],}, - {bits: 8, name: 'imm', type: 5, attr: ['8','nzuimm[5:4|9:6|2|3]']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.ADDI4SPN']}, -], config: {bits: 16}} -.... - diff --git a/src/images/wavedrom/c-ciw.edn b/src/images/wavedrom/c-ciw.edn new file mode 100644 index 0000000..b167e1f --- /dev/null +++ b/src/images/wavedrom/c-ciw.edn @@ -0,0 +1,12 @@ +//c-ciw.adoc + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C0'],}, + {bits: 3, name: 'rd′', attr: ['3','dest'],}, + {bits: 8, name: 'imm', attr: ['8','nzuimm[5:4|9:6|2|3]']}, + {bits: 3, name: 'funct3', attr: ['3','C.ADDI4SPN']}, +], config: {bits: 16}} +.... + diff --git a/src/images/wavedrom/c-cj-format-ls.adoc b/src/images/wavedrom/c-cj-format-ls.adoc deleted file mode 100644 index 1ecbd35..0000000 --- a/src/images/wavedrom/c-cj-format-ls.adoc +++ /dev/null @@ -1,23 +0,0 @@ -//c-cj-format-ls - -//[wavedrom, ,svg] -//.... -//{reg: [ -// {bits: 2, name: 'op', type: 4, attr: ['2','CI','CI']}, -// {bits: 10, name: 'imm', type: 2, }, -// {bits: 4, name: 'funct3' type: 4, attr:['3','CJ','CJAL']}, -//] config: {bits: 16}} -//.... - - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C1','C1']}, - {bits: 11, name: 'imm', type: 2, attr: ['11','offset[11|4|9:8|10|6|7|3:1|5]','offset[11|4|9:8|10|6|7|3:1|5]']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','C.J','C.JAL']}, -], config: {bits: 16}} -.... - - - diff --git a/src/images/wavedrom/c-cj-format-ls.edn b/src/images/wavedrom/c-cj-format-ls.edn new file mode 100644 index 0000000..d5fa6d1 --- /dev/null +++ b/src/images/wavedrom/c-cj-format-ls.edn @@ -0,0 +1,23 @@ +//c-cj-format-ls + +//[wavedrom, ,svg] +//.... +//{reg: [ +// {bits: 2, name: 'op', attr: ['2','CI','CI']}, +// {bits: 10, name: 'imm'}, +// {bits: 4, name: 'funct3' attr:['3','CJ','CJAL']}, +//] config: {bits: 16}} +//.... + + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C1','C1']}, + {bits: 11, name: 'imm', attr: ['11','offset[11|4|9:8|10|6|7|3:1|5]','offset[11|4|9:8|10|6|7|3:1|5]']}, + {bits: 3, name: 'funct3', attr: ['3','C.J','C.JAL']}, +], config: {bits: 16}} +.... + + + diff --git a/src/images/wavedrom/c-cr-format-ls.adoc b/src/images/wavedrom/c-cr-format-ls.adoc deleted file mode 100644 index 0329261..0000000 --- a/src/images/wavedrom/c-cr-format-ls.adoc +++ /dev/null @@ -1,12 +0,0 @@ -//These instructions use the CR format. - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C2', 'C2']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','0', '0']}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','src≠0', 'src≠0']}, - {bits: 4, name: 'funct4', type: 8, attr: ['4','C.JR', 'C.JALR']}, -], config: {bits: 16}} -.... - diff --git a/src/images/wavedrom/c-cr-format-ls.edn b/src/images/wavedrom/c-cr-format-ls.edn new file mode 100644 index 0000000..b989e2c --- /dev/null +++ b/src/images/wavedrom/c-cr-format-ls.edn @@ -0,0 +1,12 @@ +//These instructions use the CR format. + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C2', 'C2']}, + {bits: 5, name: 'rs2', attr: ['5','0', '0']}, + {bits: 5, name: 'rs1', attr: ['5','src≠0', 'src≠0']}, + {bits: 4, name: 'funct4', attr: ['4','C.JR', 'C.JALR']}, +], config: {bits: 16}} +.... + diff --git a/src/images/wavedrom/c-cs-format-ls.adoc b/src/images/wavedrom/c-cs-format-ls.adoc deleted file mode 100644 index 1f759a7..0000000 --- a/src/images/wavedrom/c-cs-format-ls.adoc +++ /dev/null @@ -1,16 +0,0 @@ -//## 16.X Load and Store Instructions -//### c-cs-format-ls - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2', 'C0','C0','C0','C0','C0']}, - {bits: 3, name: 'rs2ʹ', type: 3, attr: ['3', 'src','src','src','src','src']}, - {bits: 2, name: 'imm', type: 2, attr: ['2', 'offset[2|6]','offset[7:6]','offset[7:6]','offset[2|6]','offset[7:6]']}, - {bits: 3, name: 'rs1ʹ', type: 3, attr: ['3', 'base','base','base','base','base']}, - {bits: 3, name: 'imm', type: 3, attr: ['3', 'offset[5:3]','offset[5:3]','offset[5|4|8]','offset[5:3]','offset[5:3]']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3', 'C.SW','C.SD','C.SQ','C.FSW','C.FSD']}, -], config: {bits: 16}} -.... - - diff --git a/src/images/wavedrom/c-cs-format-ls.edn b/src/images/wavedrom/c-cs-format-ls.edn new file mode 100644 index 0000000..31f4ccf --- /dev/null +++ b/src/images/wavedrom/c-cs-format-ls.edn @@ -0,0 +1,16 @@ +//## 16.X Load and Store Instructions +//### c-cs-format-ls + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2', 'C0','C0','C0','C0','C0']}, + {bits: 3, name: 'rs2ʹ', attr: ['3', 'src','src','src','src','src']}, + {bits: 2, name: 'imm', attr: ['2', 'offset[2|6]','offset[7:6]','offset[7:6]','offset[2|6]','offset[7:6]']}, + {bits: 3, name: 'rs1ʹ', attr: ['3', 'base','base','base','base','base']}, + {bits: 3, name: 'imm', attr: ['3', 'offset[5:3]','offset[5:3]','offset[5|4|8]','offset[5:3]','offset[5:3]']}, + {bits: 3, name: 'funct3', attr: ['3', 'C.SW','C.SD','C.SQ','C.FSW','C.FSD']}, +], config: {bits: 16}} +.... + + diff --git a/src/images/wavedrom/c-def-illegal-inst.adoc b/src/images/wavedrom/c-def-illegal-inst.adoc deleted file mode 100644 index add949d..0000000 --- a/src/images/wavedrom/c-def-illegal-inst.adoc +++ /dev/null @@ -1,13 +0,0 @@ -// - -[wavedrom, ,svg] - -.... -{reg: [ - {bits: 2, name: '0', type: 8, attr: ['2','0'],}, - {bits: 5, name: '0', type: 4, attr: ['5','0'],}, - {bits: 5, name: '0', type: 8, attr: ['5','0'],}, - {bits: 1, name: '0', type: 8, attr: ['1','0'],}, - {bits: 3, name: '0', type: 8, attr: ['3','0'],}, -], config: {bits: 16}} -....
\ No newline at end of file diff --git a/src/images/wavedrom/c-def-illegal-inst.edn b/src/images/wavedrom/c-def-illegal-inst.edn new file mode 100644 index 0000000..414a19e --- /dev/null +++ b/src/images/wavedrom/c-def-illegal-inst.edn @@ -0,0 +1,13 @@ +// + +[wavedrom, ,svg] + +.... +{reg: [ + {bits: 2, name: '0', attr: ['2','0'],}, + {bits: 5, name: '0', attr: ['5','0'],}, + {bits: 5, name: '0', attr: ['5','0'],}, + {bits: 1, name: '0', attr: ['1','0'],}, + {bits: 3, name: '0', attr: ['3','0'],}, +], config: {bits: 16}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/c-int-reg-immed.adoc b/src/images/wavedrom/c-int-reg-immed.adoc deleted file mode 100644 index 45168d7..0000000 --- a/src/images/wavedrom/c-int-reg-immed.adoc +++ /dev/null @@ -1,12 +0,0 @@ -//c-int-reg-immed.adoc - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1', 'C1']}, - {bits: 5, name: 'imm[4:]', type: 1, attr: ['5','nzimm[4:0]', 'imm[4:0]', 'nzimm[4|6|8:7|5]']}, - {bits: 5, name: 'rd/rs1', type: 5, attr: ['5','dest != 0', 'dest != 0', '2']}, - {bits: 1, name: 'imm[5]', type: 5, attr: ['1','nzimm[5]', 'imm[5]', 'nzimm[9]']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.ADDI', 'C.ADDIW', 'C.ADDI16SP']}, -], config: {bits: 16}} -.... diff --git a/src/images/wavedrom/c-int-reg-immed.edn b/src/images/wavedrom/c-int-reg-immed.edn new file mode 100644 index 0000000..f509065 --- /dev/null +++ b/src/images/wavedrom/c-int-reg-immed.edn @@ -0,0 +1,12 @@ +//c-int-reg-immed.adoc + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C1', 'C1', 'C1']}, + {bits: 5, name: 'imm[4:]', attr: ['5','nzimm[4:0]', 'imm[4:0]', 'nzimm[4|6|8:7|5]']}, + {bits: 5, name: 'rd/rs1', attr: ['5','dest != 0', 'dest != 0', '2']}, + {bits: 1, name: 'imm[5]', attr: ['1','nzimm[5]', 'imm[5]', 'nzimm[9]']}, + {bits: 3, name: 'funct3', attr: ['3','C.ADDI', 'C.ADDIW', 'C.ADDI16SP']}, +], config: {bits: 16}} +.... diff --git a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc deleted file mode 100644 index b2cf982..0000000 --- a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc +++ /dev/null @@ -1,13 +0,0 @@ -// - -[wavedrom, ,svg] - -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2', 'C1', 'C1', 'C1', 'C1', 'C1', 'C1'],}, - {bits: 3, name: 'rs2′', type: 4, attr: ['3', 'src', 'src', 'src', 'src', 'src', 'src'],}, - {bits: 2, name: 'funct2', type: 8, attr: ['2', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, - {bits: 3, name: 'rd′/rs1′', type: 7, attr: ['3', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'],}, - {bits: 6, name: 'funct6', type: 8, attr: ['6', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/c-int-reg-to-reg-ca-format.edn b/src/images/wavedrom/c-int-reg-to-reg-ca-format.edn new file mode 100644 index 0000000..67e77b0 --- /dev/null +++ b/src/images/wavedrom/c-int-reg-to-reg-ca-format.edn @@ -0,0 +1,13 @@ +// + +[wavedrom, ,svg] + +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2', 'C1', 'C1', 'C1', 'C1', 'C1', 'C1'],}, + {bits: 3, name: 'rs2′', attr: ['3', 'src', 'src', 'src', 'src', 'src', 'src'],}, + {bits: 2, name: 'funct2', attr: ['2', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, + {bits: 3, name: 'rd′/rs1′', attr: ['3', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'],}, + {bits: 6, name: 'funct6', attr: ['6', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc deleted file mode 100644 index 5e607f8..0000000 --- a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc +++ /dev/null @@ -1,12 +0,0 @@ -// - -[wavedrom, ,svg] - -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2', 'C2', 'C2'],}, - {bits: 5, name: 'rs2', type: 4, attr: ['5', 'src≠0', 'src≠0'],}, - {bits: 5, name: 'rd/rs1', type: 7, attr: ['5', 'dest≠0', 'dest≠0'],}, - {bits: 4, name: 'funct4', type: 8, attr: ['4', 'C.MV', 'C.ADD'],}, -], config: {bits: 16}} -....
\ No newline at end of file diff --git a/src/images/wavedrom/c-int-reg-to-reg-cr-format.edn b/src/images/wavedrom/c-int-reg-to-reg-cr-format.edn new file mode 100644 index 0000000..ddfa0f8 --- /dev/null +++ b/src/images/wavedrom/c-int-reg-to-reg-cr-format.edn @@ -0,0 +1,12 @@ +// + +[wavedrom, ,svg] + +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2', 'C2', 'C2'],}, + {bits: 5, name: 'rs2', attr: ['5', 'src≠0', 'src≠0'],}, + {bits: 5, name: 'rd/rs1', attr: ['5', 'dest≠0', 'dest≠0'],}, + {bits: 4, name: 'funct4', attr: ['4', 'C.MV', 'C.ADD'],}, +], config: {bits: 16}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/c-integer-const-gen.adoc b/src/images/wavedrom/c-integer-const-gen.adoc deleted file mode 100644 index 732961b..0000000 --- a/src/images/wavedrom/c-integer-const-gen.adoc +++ /dev/null @@ -1,13 +0,0 @@ -//c-integer-const-gen - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1']}, - {bits: 5, name: 'imm[4:0]', type: 1, attr: ['5','imm[4:0]','imm[16:12]']}, - {bits: 5, name: 'rd', type: 5, attr: ['5','dest != 0', 'dest != {0, 2}']}, - {bits: 1, name: 'imm[5]', type: 5, attr: ['1','imm[5]', 'nzimm[17]'],}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.LI', 'C.LUI'],}, -], config: {bits: 16}} -.... - diff --git a/src/images/wavedrom/c-integer-const-gen.edn b/src/images/wavedrom/c-integer-const-gen.edn new file mode 100644 index 0000000..977ddb0 --- /dev/null +++ b/src/images/wavedrom/c-integer-const-gen.edn @@ -0,0 +1,13 @@ +//c-integer-const-gen + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C1', 'C1']}, + {bits: 5, name: 'imm[4:0]', attr: ['5','imm[4:0]','nzimm[16:12]']}, + {bits: 5, name: 'rd', attr: ['5','dest != 0', 'dest != {0, 2}']}, + {bits: 1, name: 'imm[5]', attr: ['1','imm[5]', 'nzimm[17]'],}, + {bits: 3, name: 'funct3', attr: ['3','C.LI', 'C.LUI'],}, +], config: {bits: 16}} +.... + diff --git a/src/images/wavedrom/c-mop.adoc b/src/images/wavedrom/c-mop.adoc deleted file mode 100644 index 0aee8e4..0000000 --- a/src/images/wavedrom/c-mop.adoc +++ /dev/null @@ -1,12 +0,0 @@ -[wavedrom, ,svg] -.... -{reg:[ - { bits: 2, name: 0x1, type: 8 }, - { bits: 5, name: 0x0 }, - { bits: 1, name: 0x1, type: 4 }, - { bits: 3, name: 'n[3:1]', type: 4 }, - { bits: 1, name: 0x0, type: 4 }, - { bits: 1, name: 0x0 }, - { bits: 3, name: 0x3 }, -]} -.... diff --git a/src/images/wavedrom/c-mop.edn b/src/images/wavedrom/c-mop.edn new file mode 100644 index 0000000..9b850a5 --- /dev/null +++ b/src/images/wavedrom/c-mop.edn @@ -0,0 +1,12 @@ +[wavedrom, ,svg] +.... +{reg:[ + { bits: 2, name: 0x1 }, + { bits: 5, name: 0x0 }, + { bits: 1, name: 0x1 }, + { bits: 3, name: 'n[3:1]' }, + { bits: 1, name: 0x0 }, + { bits: 1, name: 0x0 }, + { bits: 3, name: 0x3 }, +]} +.... diff --git a/src/images/wavedrom/c-nop-instr.adoc b/src/images/wavedrom/c-nop-instr.adoc deleted file mode 100644 index e3fada1..0000000 --- a/src/images/wavedrom/c-nop-instr.adoc +++ /dev/null @@ -1,13 +0,0 @@ -// - -[wavedrom, ,svg] - -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C1'],}, - {bits: 5, name: 'imm[4:0]', type: 4, attr: ['5','0'],}, - {bits: 5, name: 'rd/rs1', type: 8, attr: ['5','0'],}, - {bits: 1, name: 'imm[5]', type: 8, attr: ['1','0'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','C.NOP'],}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/c-nop-instr.edn b/src/images/wavedrom/c-nop-instr.edn new file mode 100644 index 0000000..89da752 --- /dev/null +++ b/src/images/wavedrom/c-nop-instr.edn @@ -0,0 +1,13 @@ +// + +[wavedrom, ,svg] + +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C1'],}, + {bits: 5, name: 'imm[4:0]', attr: ['5','0'],}, + {bits: 5, name: 'rd/rs1', attr: ['5','0'],}, + {bits: 1, name: 'imm[5]', attr: ['1','0'],}, + {bits: 3, name: 'funct3', attr: ['3','C.NOP'],}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/c-sp-load-store-css.adoc b/src/images/wavedrom/c-sp-load-store-css.adoc deleted file mode 100644 index 2cafcd8..0000000 --- a/src/images/wavedrom/c-sp-load-store-css.adoc +++ /dev/null @@ -1,14 +0,0 @@ -//c-sp load and store, css format--is this correct? - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C2','C2','C2','C2','C2']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','src', 'src', 'src', 'src', 'src']}, - {bits: 6, name: 'imm', type: 3, attr: ['6','offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']}, -], config: {bits: 16}} -.... - - - diff --git a/src/images/wavedrom/c-sp-load-store-css.edn b/src/images/wavedrom/c-sp-load-store-css.edn new file mode 100644 index 0000000..a398c7f --- /dev/null +++ b/src/images/wavedrom/c-sp-load-store-css.edn @@ -0,0 +1,14 @@ +//c-sp load and store, css format--is this correct? + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C2','C2','C2','C2','C2']}, + {bits: 5, name: 'rs2', attr: ['5','src', 'src', 'src', 'src', 'src']}, + {bits: 6, name: 'imm', attr: ['6','offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']}, + {bits: 3, name: 'funct3', attr: ['3','C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']}, +], config: {bits: 16}} +.... + + + diff --git a/src/images/wavedrom/c-sp-load-store.adoc b/src/images/wavedrom/c-sp-load-store.adoc deleted file mode 100644 index c39f2f6..0000000 --- a/src/images/wavedrom/c-sp-load-store.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 16.3 Load and Store Instructions -//### Stack-Pointer-Based Loads and Stores - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8, attr: ['2','C2','C2','C2','C2','C2']}, - {bits: 5, name: 'imm', type: 5, attr: ['5','offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']}, - {bits: 5, name: 'rd', type: 5, attr: ['5','dest≠0', 'dest≠0', 'dest≠0', 'dest', 'dest']}, - {bits: 1, name: 'imm', type: 1, attr: ['1','offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']}, - {bits: 3, name: 'funct3', type: 3, attr: ['3','C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']}, -], config: {bits: 16}} -.... - - diff --git a/src/images/wavedrom/c-sp-load-store.edn b/src/images/wavedrom/c-sp-load-store.edn new file mode 100644 index 0000000..f890ac8 --- /dev/null +++ b/src/images/wavedrom/c-sp-load-store.edn @@ -0,0 +1,15 @@ +//## 16.3 Load and Store Instructions +//### Stack-Pointer-Based Loads and Stores + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C2','C2','C2','C2','C2']}, + {bits: 5, name: 'imm', attr: ['5','offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']}, + {bits: 5, name: 'rd', attr: ['5','dest≠0', 'dest≠0', 'dest≠0', 'dest', 'dest']}, + {bits: 1, name: 'imm', attr: ['1','offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']}, + {bits: 3, name: 'funct3', attr: ['3','C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']}, +], config: {bits: 16}} +.... + + diff --git a/src/images/wavedrom/c-srli-srai.adoc b/src/images/wavedrom/c-srli-srai.adoc deleted file mode 100644 index 557bb39..0000000 --- a/src/images/wavedrom/c-srli-srai.adoc +++ /dev/null @@ -1,13 +0,0 @@ -//c-srli-srai.adoc - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1'],}, - {bits: 5, name: 'shamt[4:0]', type: 1, attr: ['5','shamt[4:0]', 'shamt[4:0]'],}, - {bits: 3, name: 'rd′/rs1′', type: 5, attr: ['3','dest', 'dest'],}, - {bits: 2, name: 'funct2', type: 5, attr: ['2','C.SRLI', 'C.SRAI'],}, - {bits: 1, name: 'shamt[5]', type: 5, attr: ['1','shamt[5]', 'shamt[5]'],}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','C.SRLI', 'C.SRAI'],}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/c-srli-srai.edn b/src/images/wavedrom/c-srli-srai.edn new file mode 100644 index 0000000..78a1076 --- /dev/null +++ b/src/images/wavedrom/c-srli-srai.edn @@ -0,0 +1,13 @@ +//c-srli-srai.adoc + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op', attr: ['2','C1', 'C1'],}, + {bits: 5, name: 'shamt[4:0]', attr: ['5','shamt[4:0]', 'shamt[4:0]'],}, + {bits: 3, name: 'rd′/rs1′', attr: ['3','dest', 'dest'],}, + {bits: 2, name: 'funct2', attr: ['2','C.SRLI', 'C.SRAI'],}, + {bits: 1, name: 'shamt[5]', attr: ['1','shamt[5]', 'shamt[5]'],}, + {bits: 3, name: 'funct3', attr: ['3','C.SRLI', 'C.SRAI'],}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/counters-diag.adoc b/src/images/wavedrom/counters-diag.edn index 8668162..a29d567 100644 --- a/src/images/wavedrom/counters-diag.adoc +++ b/src/images/wavedrom/counters-diag.edn @@ -4,11 +4,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','SYSTEM','SYSTEM','SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3','CSRRS','CSRRS','CSRRS'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','0','0','0'], type: 8}, - {bits: 12, name: 'csr', attr: ['12','RDCYCLE[H]', 'RDTIME[H]','RDINSTRET[H]'], type: 4}, + {bits: 7, name: 'opcode', attr: ['7','SYSTEM','SYSTEM','SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest']}, + {bits: 3, name: 'funct3', attr: ['3','CSRRS','CSRRS','CSRRS']}, + {bits: 5, name: 'rs1', attr: ['5','0','0','0']}, + {bits: 12, name: 'csr', attr: ['12','RDCYCLE[H]', 'RDTIME[H]','RDINSTRET[H]']}, ]} .... diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.adoc deleted file mode 100644 index 63286e4..0000000 --- a/src/images/wavedrom/cr-register.adoc +++ /dev/null @@ -1,112 +0,0 @@ -//# 16 "C" Standard Extension for Compressed Instructions, Version 2.0 -//## 16.2 Compressed Instruction Formats -//Table 16.1: Compressed 16-bit RVC instruction formats. -//### CR : Register - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 5, name: 'rd/rs1', type: 7}, - {bits: 4, name: 'funct4', type: 8}, - ]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'imm', type: 3}, - {bits: 5, name: 'rd/rs1', type: 7}, - {bits: 1, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 6, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rdʹ', type: 2}, - {bits: 8, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rdʹ', type: 2}, - {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1ʹ', type: 4}, - {bits: 3, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2ʹ', type: 4}, - {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1ʹ', type: 4}, - {bits: 3, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2ʹ', type: 4}, - {bits: 2, name: 'funct2', type: 8}, - {bits: 3, name: 'rdʹ/rs1ʹ', type: 7}, - {bits: 6, name: 'funct6', type: 8}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'offset', type: 3}, - {bits: 3, name: 'rdʹ/rs1ʹ', type: 7}, - {bits: 3, name: 'offset', type: 3}, - {bits: 3, name: 'funct3', type: 8}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 11, name: 'jmp trgt', type: 3}, - {bits: 3, name: 'funct3', type: 8}, -]} -.... - -//the following configuration broke the build. -//config: { -// hflip: true, -// compact: true, -// bits: 16 * 9, lanes: 9, -// margin: {right: width / 4}, -// label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS //: Store', 'CA : //Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']} -//} - - - diff --git a/src/images/wavedrom/cr-register.edn b/src/images/wavedrom/cr-register.edn new file mode 100644 index 0000000..30ad1b3 --- /dev/null +++ b/src/images/wavedrom/cr-register.edn @@ -0,0 +1,112 @@ +//# 16 "C" Standard Extension for Compressed Instructions, Version 2.0 +//## 16.2 Compressed Instruction Formats +//Table 16.1: Compressed 16-bit RVC instruction formats. +//### CR : Register + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op' }, + {bits: 5, name: 'rs2' }, + {bits: 5, name: 'rd/rs1' }, + {bits: 4, name: 'funct4' }, + ]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op' }, + {bits: 5, name: 'imm' }, + {bits: 5, name: 'rd/rs1' }, + {bits: 1, name: 'imm' }, + {bits: 3, name: 'funct3' }, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op' }, + {bits: 5, name: 'rs2' }, + {bits: 6, name: 'imm' }, + {bits: 3, name: 'funct3' }, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op' }, + {bits: 3, name: 'rdʹ' }, + {bits: 8, name: 'imm' }, + {bits: 3, name: 'funct3' }, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op' }, + {bits: 3, name: 'rdʹ' }, + {bits: 2, name: 'imm' }, + {bits: 3, name: 'rs1ʹ' }, + {bits: 3, name: 'imm' }, + {bits: 3, name: 'funct3' }, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op' }, + {bits: 3, name: 'rs2ʹ' }, + {bits: 2, name: 'imm' }, + {bits: 3, name: 'rs1ʹ' }, + {bits: 3, name: 'imm' }, + {bits: 3, name: 'funct3' }, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op' }, + {bits: 3, name: 'rs2ʹ' }, + {bits: 2, name: 'funct2' }, + {bits: 3, name: 'rdʹ/rs1ʹ' }, + {bits: 6, name: 'funct6' }, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op' }, + {bits: 5, name: 'offset' }, + {bits: 3, name: 'rdʹ/rs1ʹ' }, + {bits: 3, name: 'offset' }, + {bits: 3, name: 'funct3' }, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 2, name: 'op' }, + {bits: 11, name: 'jmp trgt' }, + {bits: 3, name: 'funct3' }, +]} +.... + +//the following configuration broke the build. +//config: { +// hflip: true, +// compact: true, +// bits: 16 * 9, lanes: 9, +// margin: {right: width / 4}, +// label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS //: Store', 'CA : //Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']} +//} + + + diff --git a/src/images/wavedrom/cr-registers-new.adoc b/src/images/wavedrom/cr-registers-new.adoc deleted file mode 100644 index 46a34e6..0000000 --- a/src/images/wavedrom/cr-registers-new.adoc +++ /dev/null @@ -1,62 +0,0 @@ -[wavedrom, ,svg] -.... -### CR : Register -${wd({reg: [ - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 5, name: 'rd / rs1ʹ, type: 7}, - {bits: 4, name: 'funct4', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'imm', type: 3}, - {bits: 5, name: 'rd / rs1', type: 7}, - {bits: 1, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 6, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rdʹ', type: 2}, - {bits: 8, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rdʹ', type: 2}, - {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1ʹ', type: 4}, - {bits: 3, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2ʹ', type: 4}, - {bits: 2, name: 'imm', type: 3}, - {bits: 3, name: 'rs1ʹ', type: 4}, - {bits: 3, name: 'imm', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 3, name: 'rs2ʹ', type: 4}, - {bits: 2, name: 'funct2', type: 8}, - {bits: 3, name: 'rd` / rs1ʹ', type: 7}, - {bits: 6, name: 'funct6', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 5, name: 'offset', type: 3}, - {bits: 3, name: 'rd` / rs1ʹ', type: 7}, - {bits: 3, name: 'offset', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - - {bits: 2, name: 'op', type: 8}, - {bits: 11, name: 'jump target', type: 3}, - {bits: 3, name: 'funct3', type: 8}, -], config: { - hflip: true, - compact: true, - bits: 16 * 9, lanes: 9, - margin: {right: width / 4}, - label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS : Store', 'CA : Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']} -}})} -.... diff --git a/src/images/wavedrom/csr-instr.adoc b/src/images/wavedrom/csr-instr.edn index 93022be..19d853e 100644 --- a/src/images/wavedrom/csr-instr.adoc +++ b/src/images/wavedrom/csr-instr.edn @@ -1,24 +1,24 @@ //# 10 "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 -//## 10.1 CSR Instructions +//## 10.1 CSR Instructions [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'source', 'source', 'source', 'uimm[4:0]', 'uimm[4:0]', 'uimm[4:0]'], type: 4}, - {bits: 12, name: 'csr', attr: ['12', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest'], type: 4}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'] }, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'] }, + {bits: 3, name: 'funct3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC', 'CSRRWI', 'CSRRSI', 'CSRRCI'] }, + {bits: 5, name: 'rs1', attr: ['5', 'source', 'source', 'source', 'uimm[4:0]', 'uimm[4:0]', 'uimm[4:0]'] }, + {bits: 12, name: 'csr', attr: ['12', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest'], }, ]} .... //[wavedrom, ,] //.... //{reg: [ -// {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM'], type: 8}, -// {bits: 5, name: 'rd', attr: ['3', 'dest','dest', 'dest' ], type: 2}, -// {bits: 3, name: 'funct3', attr: ['3', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8}, -// {bits: 5, name: 'rs1', attr: ['5', 'uimm[4:0]','uimm[4:0]', 'uimm[4:0]'], type: 3}, -// {bits: 12, name: 'csr', attr: ['12', 'source/dest','source/dest','source/dest'], type: 4}, +// {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM'] }, +// {bits: 5, name: 'rd', attr: ['3', 'dest','dest', 'dest' ] }, +// {bits: 3, name: 'funct3', attr: ['3', 'CSRRWI', 'CSRRSI', 'CSRRCI'] }, +// {bits: 5, name: 'rs1', attr: ['5', 'uimm[4:0]','uimm[4:0]', 'uimm[4:0]'] }, +// {bits: 12, name: 'csr', attr: ['12', 'source/dest','source/dest','source/dest'] }, //]} //.... diff --git a/src/images/wavedrom/ct-conditional.adoc b/src/images/wavedrom/ct-conditional.edn index b886d7c..e021907 100644 --- a/src/images/wavedrom/ct-conditional.adoc +++ b/src/images/wavedrom/ct-conditional.edn @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'BRANCH', 'BRANCH', 'BRANCH'], type: 8}, - {bits: 5, name: 'imm[4:1|11]', attr: ['5', 'offset[4:1|11]', 'offset[4:1|11]', 'offset[4:1|11]'], type: 3}, - {bits: 3, name: 'funct3', attr: ['3', 'BEQ/BNE', 'BLT[U]', 'BGE[U]'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src2','src2', 'src2'], type: 4}, - {bits: 7, name: 'imm[12|10:5]', attr: ['7', 'offset[12|10:5]', 'offset[12|10:5]', 'offset[12|10:5]'], type: 3}, + {bits: 7, name: 'opcode', attr: ['7', 'BRANCH', 'BRANCH', 'BRANCH'] }, + {bits: 5, name: 'imm[4:1|11]', attr: ['5', 'offset[4:1|11]', 'offset[4:1|11]', 'offset[4:1|11]'] }, + {bits: 3, name: 'funct3', attr: ['3', 'BEQ/BNE', 'BLT[U]', 'BGE[U]'] }, + {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1'] }, + {bits: 5, name: 'rs2', attr: ['5', 'src2','src2', 'src2'] }, + {bits: 7, name: 'imm[12|10:5]', attr: ['7', 'offset[12|10:5]', 'offset[12|10:5]', 'offset[12|10:5]'] }, ], config:{fontsize: 10}} .... diff --git a/src/images/wavedrom/ct-unconditional-2.adoc b/src/images/wavedrom/ct-unconditional-2.adoc deleted file mode 100644 index 4dda824..0000000 --- a/src/images/wavedrom/ct-unconditional-2.adoc +++ /dev/null @@ -1,12 +0,0 @@ -//ct-unconditional-2 - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'JALR'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', '0'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, -]} -.... diff --git a/src/images/wavedrom/ct-unconditional-2.edn b/src/images/wavedrom/ct-unconditional-2.edn new file mode 100644 index 0000000..95f103e --- /dev/null +++ b/src/images/wavedrom/ct-unconditional-2.edn @@ -0,0 +1,12 @@ +//ct-unconditional-2 + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'JALR'] }, + {bits: 5, name: 'rd', attr: ['5', 'dest'] }, + {bits: 3, name: 'funct3', attr: ['3', '0'] }, + {bits: 5, name: 'rs1', attr: ['5', 'base'] }, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'] }, +]} +.... diff --git a/src/images/wavedrom/ct-unconditional.adoc b/src/images/wavedrom/ct-unconditional.adoc deleted file mode 100644 index 756108f..0000000 --- a/src/images/wavedrom/ct-unconditional.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 2.5 Control Transfer Instructions -//### Unconditional Jumps - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'JAL'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 8, name: 'imm[19:12]', attr: ['8'], type: 3}, - {bits: 1, name: '[11]', attr: ['1'], type: 3}, - {bits: 10, name: 'imm[10:1]', attr: ['10', 'offset[20:1]'], type: 3}, - {bits: 1, name: '[20]', attr: ['1'], type: 3}, -], config:{fontsize: 12}} -.... - diff --git a/src/images/wavedrom/ct-unconditional.edn b/src/images/wavedrom/ct-unconditional.edn new file mode 100644 index 0000000..3dfbd94 --- /dev/null +++ b/src/images/wavedrom/ct-unconditional.edn @@ -0,0 +1,15 @@ +//## 2.5 Control Transfer Instructions +//### Unconditional Jumps + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'JAL']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 8, name: 'imm[19:12]', attr: ['8']}, + {bits: 1, name: '[11]', attr: ['1']}, + {bits: 10, name: 'imm[10:1]', attr: ['10', 'offset[20:1]']}, + {bits: 1, name: '[20]', attr: ['1']}, +], config:{fontsize: 12}} +.... + diff --git a/src/images/wavedrom/d-xwwx.adoc b/src/images/wavedrom/d-xwwx.adoc deleted file mode 100644 index 5965715..0000000 --- a/src/images/wavedrom/d-xwwx.adoc +++ /dev/null @@ -1,19 +0,0 @@ -//xw-wx - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','000','000'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FMV.X.D','FMV.D.X'], type: 8}, -]} -.... - - - - - diff --git a/src/images/wavedrom/d-xwwx.edn b/src/images/wavedrom/d-xwwx.edn new file mode 100644 index 0000000..e5fb261 --- /dev/null +++ b/src/images/wavedrom/d-xwwx.edn @@ -0,0 +1,19 @@ +//xw-wx + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','000','000']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','0','0']}, + {bits: 2, name: 'fmt', attr: ['2','D','D']}, + {bits: 5, name: 'funct5', attr: ['5','FMV.X.D','FMV.D.X']}, +]} +.... + + + + + diff --git a/src/images/wavedrom/division-op.adoc b/src/images/wavedrom/division-op.adoc deleted file mode 100644 index fabdac1..0000000 --- a/src/images/wavedrom/division-op.adoc +++ /dev/null @@ -1,25 +0,0 @@ -//## 8.2 Division Operations - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3','DIV[U]/REM[U]', 'DIV[U]W/REM[U]W'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'dividend', 'dividend'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'divisor', 'divisor'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV'], type: 8}, -]} -.... - -//[wavedrom, ,svg] -//.... -//{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-32', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: ['DIVW', 'DIVUW', 'REMW', 'REMUW'], type: 8}, -// {bits: 5, name: 'rs1', attr: 'dividend', type: 4}, -// {bits: 5, name: 'rs2', attr: 'divisor', type: 4}, -// {bits: 7, name: 'funct7', attr: 'MULDIV', type: 8}, -//]} -//.... diff --git a/src/images/wavedrom/division-op.edn b/src/images/wavedrom/division-op.edn new file mode 100644 index 0000000..0dff0e3 --- /dev/null +++ b/src/images/wavedrom/division-op.edn @@ -0,0 +1,25 @@ +//## 8.2 Division Operations + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3','DIV[U]/REM[U]', 'DIV[U]W/REM[U]W']}, + {bits: 5, name: 'rs1', attr: ['5', 'dividend', 'dividend']}, + {bits: 5, name: 'rs2', attr: ['5', 'divisor', 'divisor']}, + {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV']}, +]} +.... + +//[wavedrom, ,svg] +//.... +//{reg: [ +// {bits: 7, name: 'opcode', attr: 'OP-32'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: ['DIVW', 'DIVUW', 'REMW', 'REMUW']}, +// {bits: 5, name: 'rs1', attr: 'dividend'}, +// {bits: 5, name: 'rs2', attr: 'divisor'}, +// {bits: 7, name: 'funct7', attr: 'MULDIV'}, +//]} +//.... diff --git a/src/images/wavedrom/double-fl-class.adoc b/src/images/wavedrom/double-fl-class.adoc deleted file mode 100644 index 143ff5e..0000000 --- a/src/images/wavedrom/double-fl-class.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 13.7 Double-Precision Floating-Point Classify Instruction - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','1'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8}, -]} -.... - diff --git a/src/images/wavedrom/double-fl-class.edn b/src/images/wavedrom/double-fl-class.edn new file mode 100644 index 0000000..2779d1a --- /dev/null +++ b/src/images/wavedrom/double-fl-class.edn @@ -0,0 +1,15 @@ +//## 13.7 Double-Precision Floating-Point Classify Instruction + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','1']}, + {bits: 5, name: 'rs1', attr: ['5','src']}, + {bits: 5, name: 'rs2', attr: ['5','0']}, + {bits: 2, name: 'fmt', attr: ['2','D']}, + {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, +]} +.... + diff --git a/src/images/wavedrom/double-fl-compare.adoc b/src/images/wavedrom/double-fl-compare.adoc deleted file mode 100644 index 8403734..0000000 --- a/src/images/wavedrom/double-fl-compare.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 13.6 Double-Precision Floating-Point Compare Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8}, -]} -.... - diff --git a/src/images/wavedrom/double-fl-compare.edn b/src/images/wavedrom/double-fl-compare.edn new file mode 100644 index 0000000..550bb00 --- /dev/null +++ b/src/images/wavedrom/double-fl-compare.edn @@ -0,0 +1,15 @@ +//## 13.6 Double-Precision Floating-Point Compare Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','D']}, + {bits: 5, name: 'funct5', attr: ['5','FCMP']}, +]} +.... + diff --git a/src/images/wavedrom/double-fl-compute.adoc b/src/images/wavedrom/double-fl-compute.adoc deleted file mode 100644 index 4ce3b71..0000000 --- a/src/images/wavedrom/double-fl-compute.adoc +++ /dev/null @@ -1,54 +0,0 @@ -//## 13.4 Double-Precision Floating-Point Computational Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D','D','D','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT'], type: 8}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D'], type: 8}, - {bits: 5, name: 'rs3', attr: ['5','src3'], type: 8}, -]} -.... - -//[wavedrom, ,] -//.... -//{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: ['MIN', 'MAX'], type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 2, name: 'fmt', attr: 'D', type: 8}, -// {bits: 5, name: 'funct5', attr: 'FMIN-MAX', type: 8}, -//]} -//.... - -//[wavedrom, ,] -//.... -//{reg: [ -// {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: 'RM', type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 2, name: 'fmt', attr: 'D', type: 8}, -// {bits: 5, name: 'rs3', attr: 'src3', type: 4}, -//]} -//.... - diff --git a/src/images/wavedrom/double-fl-compute.edn b/src/images/wavedrom/double-fl-compute.edn new file mode 100644 index 0000000..8f3922d --- /dev/null +++ b/src/images/wavedrom/double-fl-compute.edn @@ -0,0 +1,54 @@ +//## 13.4 Double-Precision Floating-Point Computational Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src']}, + {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0']}, + {bits: 2, name: 'fmt', attr: ['2','D','D','D','D']}, + {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','D']}, + {bits: 5, name: 'rs3', attr: ['5','src3']}, +]} +.... + +//[wavedrom, ,] +//.... +//{reg: [ +// {bits: 7, name: 'opcode', attr: 'OP-FP'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: ['MIN', 'MAX']}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 2, name: 'fmt', attr: 'D'}, +// {bits: 5, name: 'funct5', attr: 'FMIN-MAX'}, +//]} +//.... + +//[wavedrom, ,] +//.... +//{reg: [ +// {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: 'RM'}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 2, name: 'fmt', attr: 'D'}, +// {bits: 5, name: 'rs3', attr: 'src3'}, +//]} +//.... + diff --git a/src/images/wavedrom/double-fl-convert-mv.adoc b/src/images/wavedrom/double-fl-convert-mv.adoc deleted file mode 100644 index fb23b08..0000000 --- a/src/images/wavedrom/double-fl-convert-mv.adoc +++ /dev/null @@ -1,16 +0,0 @@ -//## 13.5 Double-Precision Floating-Point Conversion and Move Instructions - - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.int.D','FCVT.D.int'], type: 8}, -]} -.... - diff --git a/src/images/wavedrom/double-fl-convert-mv.edn b/src/images/wavedrom/double-fl-convert-mv.edn new file mode 100644 index 0000000..15222d3 --- /dev/null +++ b/src/images/wavedrom/double-fl-convert-mv.edn @@ -0,0 +1,16 @@ +//## 13.5 Double-Precision Floating-Point Conversion and Move Instructions + + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]']}, + {bits: 2, name: 'fmt', attr: ['2','D','D']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.int.D','FCVT.D.int']}, +]} +.... + diff --git a/src/images/wavedrom/double-ls.adoc b/src/images/wavedrom/double-ls.adoc deleted file mode 100644 index 0c6f4dd..0000000 --- a/src/images/wavedrom/double-ls.adoc +++ /dev/null @@ -1,28 +0,0 @@ -//# "D" Standard Extension for Double-Precision Floating-Point, Version 2.2 -//## 13.3 Double-Precision Load and Store Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','LOAD-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'width', attr: ['3','D'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'], type: 3}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','STORE-FP'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]'], type: 3}, - {bits: 3, name: 'width', attr: ['3','D'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, -]} -.... - - - diff --git a/src/images/wavedrom/double-ls.edn b/src/images/wavedrom/double-ls.edn new file mode 100644 index 0000000..0191a0c --- /dev/null +++ b/src/images/wavedrom/double-ls.edn @@ -0,0 +1,28 @@ +//# "D" Standard Extension for Double-Precision Floating-Point, Version 2.2 +//## 13.3 Double-Precision Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','LOAD-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'width', attr: ['3','D']}, + {bits: 5, name: 'rs1', attr: ['5','base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]']}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','STORE-FP']}, + {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]']}, + {bits: 3, name: 'width', attr: ['3','D']}, + {bits: 5, name: 'rs1', attr: ['5','base']}, + {bits: 5, name: 'rs2', attr: ['5','src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]']}, +]} +.... + + + diff --git a/src/images/wavedrom/env-call-breakpoint.edn b/src/images/wavedrom/env-call-breakpoint.edn new file mode 100644 index 0000000..5814faf --- /dev/null +++ b/src/images/wavedrom/env-call-breakpoint.edn @@ -0,0 +1,12 @@ +//## 2.8 Environment Call and Breakpoints + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', '0', '0']}, + {bits: 12, name: 'func12', attr: ['12', 'ECALL', 'EBREAK']}, +]} +.... diff --git a/src/images/wavedrom/env_call-breakpoint.adoc b/src/images/wavedrom/env_call-breakpoint.adoc deleted file mode 100644 index 7812687..0000000 --- a/src/images/wavedrom/env_call-breakpoint.adoc +++ /dev/null @@ -1,12 +0,0 @@ -//## 2.8 Environment Call and Breakpoints - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0', '0'], type: 4}, - {bits: 12, name: 'func12', attr: ['12', 'ECALL', 'EBREAK'], type: 8}, -]} -.... diff --git a/src/images/wavedrom/fcvt-sd-ds.adoc b/src/images/wavedrom/fcvt-sd-ds.adoc deleted file mode 100644 index 5b68a54..0000000 --- a/src/images/wavedrom/fcvt-sd-ds.adoc +++ /dev/null @@ -1,16 +0,0 @@ -//FCVT.S.D and FCVT.D.S - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','D', 'S'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.S.D', 'FCVT.D.S'], type: 8}, -]} -.... - - diff --git a/src/images/wavedrom/fcvt-sd-ds.edn b/src/images/wavedrom/fcvt-sd-ds.edn new file mode 100644 index 0000000..a192ffa --- /dev/null +++ b/src/images/wavedrom/fcvt-sd-ds.edn @@ -0,0 +1,16 @@ +//FCVT.S.D and FCVT.D.S + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','D', 'S']}, + {bits: 2, name: 'fmt', attr: ['2','S','D']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.S.D', 'FCVT.D.S']}, +]} +.... + + diff --git a/src/images/wavedrom/float-csr.adoc b/src/images/wavedrom/float-csr.adoc deleted file mode 100644 index 7b2cf24..0000000 --- a/src/images/wavedrom/float-csr.adoc +++ /dev/null @@ -1,17 +0,0 @@ -//# "F" Standard Extension for Single-Precision Floating-Point, Version 2.2 -//## 12.2 Floating-Point Control and Status Register -//### Figure 12.2: Floating-point control and status register. - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: 'NX', attr: ['1'], type: 5}, - {bits: 1, name: 'UF', attr: ['1'], type: 5}, - {bits: 1, name: 'OF', attr: ['1'], type: 5}, - {bits: 1, name: 'DZ', attr: ['1'], type: 5}, - {bits: 1, name: 'NV', attr: ['1'], type: 5}, - {bits: 3, name: 'Rounding Mode', attr:['3'], type: 6}, - {bits: 24, name: 'Reserved', attr:['24'], type: 7}, -], config: {fontsize: 10}} -.... - diff --git a/src/images/wavedrom/float-csr.edn b/src/images/wavedrom/float-csr.edn new file mode 100644 index 0000000..56be164 --- /dev/null +++ b/src/images/wavedrom/float-csr.edn @@ -0,0 +1,17 @@ +//# "F" Standard Extension for Single-Precision Floating-Point, Version 2.2 +//## 12.2 Floating-Point Control and Status Register +//### Figure 12.2: Floating-point control and status register. + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'NX', attr: ['1']}, + {bits: 1, name: 'UF', attr: ['1']}, + {bits: 1, name: 'OF', attr: ['1']}, + {bits: 1, name: 'DZ', attr: ['1']}, + {bits: 1, name: 'NV', attr: ['1']}, + {bits: 3, name: 'Rounding Mode', attr:['3']}, + {bits: 24, name: 'Reserved', attr:['24']}, +], config: {fontsize: 10}} +.... + diff --git a/src/images/wavedrom/flt-pt-to-int-move.adoc b/src/images/wavedrom/flt-pt-to-int-move.adoc deleted file mode 100644 index fc2a95a..0000000 --- a/src/images/wavedrom/flt-pt-to-int-move.adoc +++ /dev/null @@ -1,14 +0,0 @@ -// 16.3 Instructions for moving bit patterns between floating-point and integer registers. - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','000','000'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H','H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FMV.X.H','FMV.H.X'], type: 8}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/flt-pt-to-int-move.edn b/src/images/wavedrom/flt-pt-to-int-move.edn new file mode 100644 index 0000000..861085e --- /dev/null +++ b/src/images/wavedrom/flt-pt-to-int-move.edn @@ -0,0 +1,14 @@ +// 16.3 Instructions for moving bit patterns between floating-point and integer registers. + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','000','000']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','0','0']}, + {bits: 2, name: 'fmt', attr: ['2','H','H']}, + {bits: 5, name: 'funct5', attr: ['5','FMV.X.H','FMV.H.X']}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc deleted file mode 100644 index 43250a4..0000000 --- a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc +++ /dev/null @@ -1,14 +0,0 @@ -// 16.3 Floating point to floating point sign injection instructions. - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3','J[N]/JX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FSGNJ'], type: 8}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn new file mode 100644 index 0000000..830cb2a --- /dev/null +++ b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn @@ -0,0 +1,14 @@ +// 16.3 Floating point to floating point sign injection instructions. + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'funct3', attr: ['3','J[N]/JX']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','H']}, + {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/fnmaddsub.adoc b/src/images/wavedrom/fnmaddsub.adoc deleted file mode 100644 index e8bda1b..0000000 --- a/src/images/wavedrom/fnmaddsub.adoc +++ /dev/null @@ -1,16 +0,0 @@ - -//FNMSUP and FNMADD - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, - {bits: 5, name: 'rd', attr: 'dest', type: 2}, - {bits: 3, name: 'funct3', attr: 'RM', type: 8}, - {bits: 5, name: 'rs1', attr: 'src1', type: 4}, - {bits: 5, name: 'rs2', attr: 'src2', type: 4}, - {bits: 2, name: 'fmt', attr: 'S', type: 8}, - {bits: 5, name: 'rs3', attr: 'src3', type: 4}, -]} -.... - diff --git a/src/images/wavedrom/fsjgnjnx-d.adoc b/src/images/wavedrom/fsjgnjnx-d.adoc deleted file mode 100644 index fff7808..0000000 --- a/src/images/wavedrom/fsjgnjnx-d.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//FSGNJ.D, FSGNJN.D, and FSGNJX.D - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','J[N]/JX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','D'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FSGNJ'], type: 8}, -]} -.... - diff --git a/src/images/wavedrom/fsjgnjnx-d.edn b/src/images/wavedrom/fsjgnjnx-d.edn new file mode 100644 index 0000000..6247a94 --- /dev/null +++ b/src/images/wavedrom/fsjgnjnx-d.edn @@ -0,0 +1,15 @@ +//FSGNJ.D, FSGNJN.D, and FSGNJX.D + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','J[N]/JX']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','D']}, + {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, +]} +.... + diff --git a/src/images/wavedrom/half-ls.adoc b/src/images/wavedrom/half-ls.adoc deleted file mode 100644 index fb26d9b..0000000 --- a/src/images/wavedrom/half-ls.adoc +++ /dev/null @@ -1,14 +0,0 @@ -//## 15.1 Half-Precision Load and Store Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: 'LOAD-FP', type: 8}, - {bits: 5, name: 'rd', attr: 'dest', type: 2}, - {bits: 3, name: 'width', attr: 'H', type: 8}, - {bits: 5, name: 'rs1', attr: 'base', type: 4}, - {bits: 12, name: 'imm[11:0]', attr: 'offset', type: 3}, -]} - -.... - diff --git a/src/images/wavedrom/half-ls.edn b/src/images/wavedrom/half-ls.edn new file mode 100644 index 0000000..1d74b69 --- /dev/null +++ b/src/images/wavedrom/half-ls.edn @@ -0,0 +1,14 @@ +//## 15.1 Half-Precision Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'LOAD-FP'}, + {bits: 5, name: 'rd', attr: 'dest'}, + {bits: 3, name: 'width', attr: 'H'}, + {bits: 5, name: 'rs1', attr: 'base'}, + {bits: 12, name: 'imm[11:0]', attr: 'offset'}, +]} + +.... + diff --git a/src/images/wavedrom/half-pr-flt-pt-class.adoc b/src/images/wavedrom/half-pr-flt-pt-class.adoc deleted file mode 100644 index 5490f5e..0000000 --- a/src/images/wavedrom/half-pr-flt-pt-class.adoc +++ /dev/null @@ -1,14 +0,0 @@ -//## 15.5 Half-Precision Floating-Point Classify Instruction - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','001'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/half-pr-flt-pt-class.edn b/src/images/wavedrom/half-pr-flt-pt-class.edn new file mode 100644 index 0000000..d2af321 --- /dev/null +++ b/src/images/wavedrom/half-pr-flt-pt-class.edn @@ -0,0 +1,14 @@ +//## 15.5 Half-Precision Floating-Point Classify Instruction + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','001']}, + {bits: 5, name: 'rs1', attr: ['5', 'src']}, + {bits: 5, name: 'rs2', attr: ['5','0']}, + {bits: 2, name: 'fmt', attr: ['2','H']}, + {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/half-pr-flt-pt-compare.adoc b/src/images/wavedrom/half-pr-flt-pt-compare.adoc deleted file mode 100644 index 78033c1..0000000 --- a/src/images/wavedrom/half-pr-flt-pt-compare.adoc +++ /dev/null @@ -1,14 +0,0 @@ -// 16.4 Half-Precision Floating-Point Compare Instructions. - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/half-pr-flt-pt-compare.edn b/src/images/wavedrom/half-pr-flt-pt-compare.edn new file mode 100644 index 0000000..47e2e9f --- /dev/null +++ b/src/images/wavedrom/half-pr-flt-pt-compare.edn @@ -0,0 +1,14 @@ +// 16.4 Half-Precision Floating-Point Compare Instructions. + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','H']}, + {bits: 5, name: 'funct5', attr: ['5','FCMP']}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/half-prec-conv-and-mv.adoc b/src/images/wavedrom/half-prec-conv-and-mv.adoc deleted file mode 100644 index 013f1b9..0000000 --- a/src/images/wavedrom/half-prec-conv-and-mv.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 16.3 Half-Precision Conversion and Move Instructions - - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]'], type: 3}, - {bits: 2, name: 'fmt', attr: ['2','H', 'H'], type: 2}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.int.H','FCVT.H.int'], type: 8}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/half-prec-conv-and-mv.edn b/src/images/wavedrom/half-prec-conv-and-mv.edn new file mode 100644 index 0000000..7f05de4 --- /dev/null +++ b/src/images/wavedrom/half-prec-conv-and-mv.edn @@ -0,0 +1,15 @@ +//## 16.3 Half-Precision Conversion and Move Instructions + + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]']}, + {bits: 2, name: 'fmt', attr: ['2','H', 'H']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.int.H','FCVT.H.int']}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.edn index c42038c..f95854d 100644 --- a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc +++ b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.edn @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src','src','src','src','SRC'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','H','S','H','D','H','Q'], type: 3}, - {bits: 2, name: 'fmt', attr: ['2','S','H','D','H','Q','H'], type: 2}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.S.H','FCVT.H.S','FCVT.D.H','FCVT.H.D','FCVT.Q.H','FCVT.H.Q'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src','src','src','src','SRC']}, + {bits: 5, name: 'rs2', attr: ['5','H','S','H','D','H','Q']}, + {bits: 2, name: 'fmt', attr: ['2','S','H','D','H','Q','H']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.S.H','FCVT.H.S','FCVT.D.H','FCVT.H.D','FCVT.Q.H','FCVT.H.Q']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/half-store.adoc b/src/images/wavedrom/half-store.adoc deleted file mode 100644 index fb0d18c..0000000 --- a/src/images/wavedrom/half-store.adoc +++ /dev/null @@ -1,11 +0,0 @@ -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: 'STORE-FP', type: 8}, - {bits: 5, name: 'imm[4:0]', attr: 'offset', type: 3}, - {bits: 3, name: 'width', attr: 'H', type: 8}, - {bits: 5, name: 'rs1', attr: 'base', type: 4}, - {bits: 5, name: 'rs2', attr: 'src', type: 4}, - {bits: 12, name: 'imm[11:5]', attr: 'offset', type: 3}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/hint-nopv_rv32i.adoc b/src/images/wavedrom/hint-nopv_rv32i.adoc deleted file mode 100644 index b26a6d1..0000000 --- a/src/images/wavedrom/hint-nopv_rv32i.adoc +++ /dev/null @@ -1,55 +0,0 @@ -//### RV32I -//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (2.9) -//{ADDI, SLTI, SLTIU, XORI, ORI, ANDI} x0, ? ( ${ 6 * 1 << 17} ) -[wavedrom, ,svg] -.... -{reg: [ - {name: 'OP-IMM', bits: 7, attr: 0b0010011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['ADDI', 'SLTI', 'SLTIU', 'XORI', 'ORI', 'ANDI']}, - {bits: 17} -], config: {hspace: width}} -.... -//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP-IMM', bits: 7, attr: 0b0010011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']}, - {bits: 10}, - {name: 'imm?', bits: 7, attr: [0, 0, 32]} -], config: {hspace: width}} -.... -//{LUI, AUIPC} x0, ? ( ${ 2 * (1 << 20) } ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'opcode', bits: 7, attr: ['AUIPC', 'LUI']}, - {name: 'rd', bits: 5, attr: 0}, - {bits: 20} -], config: {hspace: width}} -.... -//{ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND} x0, ?, ? ( ${ 10 * 1 << 10} ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP', bits: 7, attr: 0b0110011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: 'ADD SUB SLL SLT SLTU XOR SRL SRA OR AND'.split(' ', - {bits: 10}, - {name: 'funct7', bits: 7, attr: [0, 0, 0, 0, 0, 0, 32, 32, 0, 0]} -], config: {hspace: width}} -.... - -//RV32I_extra = ( -// 3 * 31 + -// 31 + -// 7 * 31 + -// 3 * 31 + -// 2 * 31 -//) - diff --git a/src/images/wavedrom/hint-nopv_rv64i.adoc b/src/images/wavedrom/hint-nopv_rv64i.adoc deleted file mode 100644 index ee78cf8..0000000 --- a/src/images/wavedrom/hint-nopv_rv64i.adoc +++ /dev/null @@ -1,57 +0,0 @@ -//### RV64I -//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (4.4) -//All RV32I NOPs plus: -//ADDIW x0, ? ( ${ 1 << 17 } ) -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP-IMM-32', bits: 7, attr: 0b0011011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: 'ADDIW'}, - {bits: 17} -], config: {hspace: width}} -.... -//Extra bit for the shift ammont: -//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} ) - -[wavedrom, ,svg] -.... -{reg: [ - {name: 'OP-IMM', bits: 7, attr: 0b0010011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']}, - {bits: 10}, - {name: 'imm?', bits: 7, attr: [1, 33, 33]} -], config: {hspace: width}} -.... -//{SLLIW, SRLIW, SRAIW} x0, ?( ${ 3 * 1 << 10} ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP-IMM-32', bits: 7, attr: 0b0011011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['SLLIW', 'SRLIW', 'SRAIW']}, - {bits: 10}, - {name: 'imm?', bits: 7, attr: [0, 32, 32]} -], config: {hspace: width}} -.... -//SLL, SLT, SRA ( ??? ) -//{ADDW, SLLW, SRLW, SUBW, SRAW} x0, ?, ? ( ${ 5 * 1 << 10 } ) - -[wavedrom, ,svg] -.... -{reg:[ - {name: 'OP-32', bits: 7, attr: 0b0111011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']}, - {bits: 10}, - {name: 'funct7', bits: 7, attr: [0, 0, 32, 0, 32]} -], config: {hspace: width}} -.... - -//RV64I_extra = ( -// 4 * 31 + -// 5 * 31 + -// 31 -//` diff --git a/src/images/wavedrom/hinvalgvma.edn b/src/images/wavedrom/hinvalgvma.edn index ab1a0cd..d3f9dd9 100644 --- a/src/images/wavedrom/hinvalgvma.edn +++ b/src/images/wavedrom/hinvalgvma.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'gaddr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'vmid'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.GVMA'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', 'gaddr']}, + {bits: 5, name: 'rs2', attr: ['5', 'vmid']}, + {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.GVMA']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/hinvalvvma.edn b/src/images/wavedrom/hinvalvvma.edn index 0b93b9f..05f5d40 100644 --- a/src/images/wavedrom/hinvalvvma.edn +++ b/src/images/wavedrom/hinvalvvma.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'vaddr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'asid'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.VVMA'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', 'vaddr']}, + {bits: 5, name: 'rs2', attr: ['5', 'asid']}, + {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.VVMA']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/hypv-mm-fence.edn b/src/images/wavedrom/hypv-mm-fence.edn index 2840b1a..a653d4e 100644 --- a/src/images/wavedrom/hypv-mm-fence.edn +++ b/src/images/wavedrom/hypv-mm-fence.edn @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 3, attr: ['7', 'SYSTEM', 'SYSTEM']}, - {bits: 5, name: 'rd', type: 5, attr: ['5','0', '0']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','PRIV', 'PRIV']}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','vaddr', 'gaddr']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','asid', 'vmid']}, - {bits: 7, name: 'funct7', type: 5, attr: ['7','HFENCE.VVMA', 'HFENCE.GVMA']}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5','0', '0']}, + {bits: 3, name: 'funct3', attr: ['3','PRIV', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5','vaddr', 'gaddr']}, + {bits: 5, name: 'rs2', attr: ['5','asid', 'vmid']}, + {bits: 7, name: 'funct7', attr: ['7','HFENCE.VVMA', 'HFENCE.GVMA']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/hypv-virt-load-and-store.edn b/src/images/wavedrom/hypv-virt-load-and-store.edn index d0e1d9e..2ee4486 100644 --- a/src/images/wavedrom/hypv-virt-load-and-store.edn +++ b/src/images/wavedrom/hypv-virt-load-and-store.edn @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 3, attr: ['7','SYSTEM', 'SYSTEM', 'SYSTEM']}, - {bits: 5, name: 'rd', type: 5, attr: ['5','dest', 'dest', '0']}, - {bits: 3, name: 'funct3', type: 5, attr: ['3','PRIVM', 'PRIVM', 'PRIVM']}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','addr', 'addr', 'addr']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5','[U]', 'HLVX', 'src']}, - {bits: 7, name: 'funct7', type: 5, attr: ['7','HLV.width', 'HLVX.HU/WU', 'HSV.width']}, + {bits: 7, name: 'opcode', attr: ['7','SYSTEM', 'SYSTEM', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5','dest', 'dest', '0']}, + {bits: 3, name: 'funct3', attr: ['3','PRIVM', 'PRIVM', 'PRIVM']}, + {bits: 5, name: 'rs1', attr: ['5','addr', 'addr', 'addr']}, + {bits: 5, name: 'rs2', attr: ['5','[U]', 'HLVX', 'src']}, + {bits: 7, name: 'funct7', attr: ['7','HLV.width', 'HLVX.HU/WU', 'HSV.width']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/i-immediate.edn b/src/images/wavedrom/i-immediate.edn new file mode 100644 index 0000000..578b0e3 --- /dev/null +++ b/src/images/wavedrom/i-immediate.edn @@ -0,0 +1,14 @@ +//### Figure 2.4 +//Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31]. +//#### I-immediate + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: '[20]'}, + {bits: 4, name: 'inst[24:21]'}, + {bits: 6, name: 'inst[30:25]'}, + {bits: 21, name: '— inst[31] —'}, +], config:{fontsize: 12, label:{right: 'I-immediate'}}} +.... + diff --git a/src/images/wavedrom/immediate_variants.adoc b/src/images/wavedrom/immediate-variants.edn index c1f8335..8f9be0c 100644 --- a/src/images/wavedrom/immediate_variants.adoc +++ b/src/images/wavedrom/immediate-variants.edn @@ -21,7 +21,7 @@ {bits: 5, name: 'rd'}, {bits: 3, name: 'funct3'}, {bits: 5, name: 'rs1'}, - {bits: 12, name: 'imm[11:0]', type: 3}, + {bits: 12, name: 'imm[11:0]'}, ], config: {label: {right: 'I-Type'}}} .... @@ -29,11 +29,11 @@ .... {reg: [ {bits: 7, name: 'opcode'}, - {bits: 5, name: 'imm[4:0]', type: 3}, + {bits: 5, name: 'imm[4:0]'}, {bits: 3, name: 'funct3'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, - {bits: 7, name: 'imm[11:5]', type: 3} + {bits: 7, name: 'imm[11:5]'} ], config: {label: {right: 'S-Type'}}} .... @@ -41,13 +41,13 @@ .... {reg: [ {bits: 7, name: 'opcode'}, - {bits: 1, name: '[11]', type: 3}, - {bits: 4, name: 'imm[4:1]', type: 3}, + {bits: 1, name: '[11]'}, + {bits: 4, name: 'imm[4:1]'}, {bits: 3, name: 'funct3'}, {bits: 5, name: 'rs1'}, {bits: 5, name: 'rs2'}, - {bits: 6, name: 'imm[10:5]', type: 3}, - {bits: 1, name: '[12]', type: 3} + {bits: 6, name: 'imm[10:5]'}, + {bits: 1, name: '[12]'} ], config: {fontsize: 12, label: {right: 'B-Type'}}} .... @@ -56,7 +56,7 @@ {reg: [ {bits: 7, name: 'opcode'}, {bits: 5, name: 'rd'}, - {bits: 20, name: 'imm[31:12]', type: 3} + {bits: 20, name: 'imm[31:12]'} ], config: {label: {right: 'U-Type'}}} .... @@ -65,10 +65,10 @@ {reg: [ {bits: 7, name: 'opcode'}, {bits: 5, name: 'rd'}, - {bits: 8, name: 'imm[19:12]', type: 3}, - {bits: 1, name: '[11]', type: 3}, - {bits: 10, name: 'imm[10:1]', type: 3}, - {bits: 1, name: '[20]', type: 3} + {bits: 8, name: 'imm[19:12]'}, + {bits: 1, name: '[11]'}, + {bits: 10, name: 'imm[10:1]'}, + {bits: 1, name: '[20]'} ], config: {fontsize: 12, label: {right: 'J-Type'}}} .... diff --git a/src/images/wavedrom/immediate.adoc b/src/images/wavedrom/immediate.adoc deleted file mode 100644 index c6fb00d..0000000 --- a/src/images/wavedrom/immediate.adoc +++ /dev/null @@ -1,60 +0,0 @@ -//### Figure 2.4 -//Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31]. -//#### I-immediate - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: '[20]'}, - {bits: 4, name: 'inst[24:21]'}, - {bits: 6, name: 'inst[30:25]'}, - {bits: 21, name: '— inst[31] —', type: 7}, -], config:{fontsize: 12, label:{right: 'I-immediate'}}} -.... -//#### S-immediate - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: '[7]'}, - {bits: 4, name: 'inst[11:8]'}, - {bits: 6, name: 'inst[30:25]'}, - {bits: 21, name: '— inst[31] —', type: 7}, -], config:{fontsize: 12, label:{right: 'S-immediate'}}} -.... -//#### B-immediate - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: '0', type: 5}, - {bits: 4, name: 'inst[11:8]'}, - {bits: 6, name: 'inst[30:25]'}, - {bits: 1, name: '[7]'}, - {bits: 20, name: '— inst[31] —', type: 7}, -], config:{fontsize: 12, label:{right: 'B-immediate'}}} -.... -//#### U-immediate - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 12, name: '0', type: 5}, - {bits: 8, name: 'inst[19:12]'}, - {bits: 11, name: 'inst[30:20]'}, - {bits: 1, name: '[31]', type: 7}, -], config:{fontsize: 12, label:{right: 'U-immediate'}}} -.... -//#### J-immediate - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 1, name: '0', type: 5}, - {bits: 4, name: 'inst[24:21]'}, - {bits: 6, name: 'inst[30:25]'}, - {bits: 1, name: '[20]'}, - {bits: 8, name: 'inst[19:12]'}, - {bits: 12, name: '— inst[31] —', type: 7}, -], config:{fontsize: 12, label:{right: 'J-immediate'}}} -.... diff --git a/src/images/wavedrom/immediate.edn b/src/images/wavedrom/immediate.edn new file mode 100644 index 0000000..e8a034a --- /dev/null +++ b/src/images/wavedrom/immediate.edn @@ -0,0 +1,17 @@ +//### Figure 2.4 +//Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31]. +//#### I-immediate + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: '[20]'}, + {bits: 4, name: 'inst[24:21]'}, + {bits: 6, name: 'inst[30:25]'}, + {bits: 21, name: '— inst[31] —'}, +], config:{fontsize: 12, label:{right: 'I-immediate'}}} +.... + + + + diff --git a/src/images/wavedrom/immediate_variants2.adoc b/src/images/wavedrom/immediate_variants2.adoc deleted file mode 100644 index 498b282..0000000 --- a/src/images/wavedrom/immediate_variants2.adoc +++ /dev/null @@ -1,56 +0,0 @@ -## 2.3 Immediate Encoding Variants -### Figure 2.3 - -RISC-V base instruction formats showing immediate variants. - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 3, name: 'func3'}, - {bits: 5, name: 'rs1'}, - {bits: 5, name: 'rs2'}, - {bits: 7, name: 'funct7'} -], config: {label: {right: 'R-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 3, name: 'func3'}, - {bits: 5, name: 'rs1'}, - {bits: 12, name: 'imm[11:0]', type: 3}, -], config: {label: {right: 'I-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'imm[4:0]', type: 3}, - {bits: 3, name: 'func3'}, - {bits: 5, name: 'rs1'}, - {bits: 5, name: 'rs2'}, - {bits: 7, name: 'imm[11:5]', type: 3} -], config: {label: {right: 'S-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 1, name: '[11]', type: 3}, - {bits: 4, name: 'imm[4:1]', type: 3}, - {bits: 3, name: 'func3'}, - {bits: 5, name: 'rs1'}, - {bits: 5, name: 'rs2'}, - {bits: 6, name: 'imm[10:5]', type: 3}, - {bits: 1, name: '[12]', type: 3} -], config: {label: {right: 'B-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 20, name: 'imm[31:12]', type: 3} -], config: {label: {right: 'U-Type'}}})} - -${wd({reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 8, name: 'imm[19:12]', type: 3}, - {bits: 1, name: '[11]', type: 3}, - {bits: 10, name: 'imm[10:1]', type: 3}, - {bits: 1, name: '[20]', type: 3} -], config: {label: {right: 'J-Type'}}})}
\ No newline at end of file diff --git a/src/images/wavedrom/instruction-formats.edn b/src/images/wavedrom/instruction-formats.edn new file mode 100644 index 0000000..0741210 --- /dev/null +++ b/src/images/wavedrom/instruction-formats.edn @@ -0,0 +1,48 @@ +//### Figure 2.2 + +//RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done. + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode'}, + {bits: 5, name: 'rd'}, + {bits: 3, name: 'funct3'}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, + {bits: 7, name: 'funct7'} +], config: {label: {right: 'R-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode'}, + {bits: 5, name: 'rd'}, + {bits: 3, name: 'funct3'}, + {bits: 5, name: 'rs1'}, + {bits: 12, name: 'imm[11:0]'}, +], config: {label: {right: 'I-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode'}, + {bits: 5, name: 'imm[4:0]'}, + {bits: 3, name: 'funct3'}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, + {bits: 7, name: 'imm[11:5]'} +], config: {label: {right: 'S-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode'}, + {bits: 5, name: 'rd'}, + {bits: 20, name: 'imm[31:12]'} +], config: {label: {right: 'U-Type'}}} +.... + diff --git a/src/images/wavedrom/instruction_formats.adoc b/src/images/wavedrom/instruction_formats.adoc deleted file mode 100644 index 442e27d..0000000 --- a/src/images/wavedrom/instruction_formats.adoc +++ /dev/null @@ -1,48 +0,0 @@ -//### Figure 2.2 - -//RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done. - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 5, name: 'rd', type: 2}, - {bits: 3, name: 'funct3', type: 8}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 7, name: 'funct7', type: 8} -], config: {label: {right: 'R-Type'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 5, name: 'rd', type: 2}, - {bits: 3, name: 'funct3', type: 8}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 12, name: 'imm[11:0]', type: 3}, -], config: {label: {right: 'I-Type'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 5, name: 'imm[4:0]', type: 3}, - {bits: 3, name: 'funct3', type: 8}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 7, name: 'imm[11:5]', type: 3} -], config: {label: {right: 'S-Type'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 5, name: 'rd', type: 2}, - {bits: 20, name: 'imm[31:12]', type: 3} -], config: {label: {right: 'U-Type'}}} -.... - diff --git a/src/images/wavedrom/int-comp-lui-aiupc.adoc b/src/images/wavedrom/int-comp-lui-aiupc.edn index c3dbf95..dfb77d1 100644 --- a/src/images/wavedrom/int-comp-lui-aiupc.adoc +++ b/src/images/wavedrom/int-comp-lui-aiupc.edn @@ -5,8 +5,8 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]'], type: 3} + {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]']} ]} .... diff --git a/src/images/wavedrom/int-comp-slli-srli-srai.adoc b/src/images/wavedrom/int-comp-slli-srli-srai.edn index 3fa49a4..3e86d08 100644 --- a/src/images/wavedrom/int-comp-slli-srli-srai.adoc +++ b/src/images/wavedrom/int-comp-slli-srli-srai.edn @@ -5,12 +5,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src'], type: 4}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]'], type: 3}, - {bits: 7, name: 'imm[11:5]', attr: ['7', 0, 0, 32], type: 8} + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI']}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]']}, + {bits: 7, name: 'imm[11:5]', attr: ['7', 0, 0, 32]} ]} .... diff --git a/src/images/wavedrom/int_reg-reg.adoc b/src/images/wavedrom/int-reg-reg.edn index 1ec0c17..3fd19f7 100644 --- a/src/images/wavedrom/int_reg-reg.adoc +++ b/src/images/wavedrom/int-reg-reg.edn @@ -3,11 +3,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP', 'OP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest','dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'ADD/SLT[U]', 'AND/OR/XOR', 'SLL/SRL', 'SUB/SRA'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 0, 0, 0, 32], type: 8} + {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP', 'OP']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest','dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'ADD/SLT[U]', 'AND/OR/XOR', 'SLL/SRL', 'SUB/SRA']}, + {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1']}, + {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2']}, + {bits: 7, name: 'funct7', attr: ['7', 0, 0, 0, 32]} ]} .... diff --git a/src/images/wavedrom/integer-computational.edn b/src/images/wavedrom/integer-computational.edn new file mode 100644 index 0000000..707f06f --- /dev/null +++ b/src/images/wavedrom/integer-computational.edn @@ -0,0 +1,15 @@ +//## 2.4 Integer Computational Instructions +//### Integer Register-Immediate Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'ADDI/SLTI[U]', 'ANDI/ORI/XORI']}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]', 'I-immediate[11:0]']} +]} +.... + +//<snio> diff --git a/src/images/wavedrom/integer_computational.adoc b/src/images/wavedrom/integer_computational.adoc deleted file mode 100644 index 5172d4e..0000000 --- a/src/images/wavedrom/integer_computational.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 2.4 Integer Computational Instructions -//### Integer Register-Immediate Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'ADDI/SLTI[U]', 'ANDI/ORI/XORI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src', 'src'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]', 'I-immediate[11:0]'], type: 3} -]} -.... - -//<snio> diff --git a/src/images/wavedrom/j-immediate.edn b/src/images/wavedrom/j-immediate.edn new file mode 100644 index 0000000..dbeddd9 --- /dev/null +++ b/src/images/wavedrom/j-immediate.edn @@ -0,0 +1,13 @@ +//#### J-immediate + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: '0'}, + {bits: 4, name: 'inst[24:21]'}, + {bits: 6, name: 'inst[30:25]'}, + {bits: 1, name: '[20]'}, + {bits: 8, name: 'inst[19:12]'}, + {bits: 12, name: '— inst[31] —'}, +], config:{fontsize: 12, label:{right: 'J-immediate'}}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/load-reserve-st-conditional.adoc b/src/images/wavedrom/load-reserve-st-conditional.adoc deleted file mode 100644 index 355342c..0000000 --- a/src/images/wavedrom/load-reserve-st-conditional.adoc +++ /dev/null @@ -1,19 +0,0 @@ -//# 9 "A" Standard Extension for Atomic Instructions, Version 2.1 -//## 9.2 Load-Reserved/Store-Conditional Instructions - - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'AMO', 'AMO'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'width', 'width'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'addr', 'addr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', '0', 'src'], type: 4}, - {bits: 1, name: 'rl', attr: ['1', 'ring', 'ring'], type: 8}, - {bits: 1, name: 'aq', attr: ['1', 'orde', 'orde'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5', 'LR.W/D', 'SC.W/D'], type: 8}, -]} -.... - - diff --git a/src/images/wavedrom/load-reserve-st-conditional.edn b/src/images/wavedrom/load-reserve-st-conditional.edn new file mode 100644 index 0000000..c1addd3 --- /dev/null +++ b/src/images/wavedrom/load-reserve-st-conditional.edn @@ -0,0 +1,19 @@ +//# 9 "A" Standard Extension for Atomic Instructions, Version 2.1 +//## 9.2 Load-Reserved/Store-Conditional Instructions + + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'AMO', 'AMO']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'width', 'width']}, + {bits: 5, name: 'rs1', attr: ['5', 'addr', 'addr']}, + {bits: 5, name: 'rs2', attr: ['5', '0', 'src']}, + {bits: 1, name: 'rl', attr: ['1', 'ring', 'ring']}, + {bits: 1, name: 'aq', attr: ['1', 'orde', 'orde']}, + {bits: 5, name: 'funct5', attr: ['5', 'LR.W/D', 'SC.W/D']}, +]} +.... + + diff --git a/src/images/wavedrom/load-store.edn b/src/images/wavedrom/load-store.edn new file mode 100644 index 0000000..ac23d35 --- /dev/null +++ b/src/images/wavedrom/load-store.edn @@ -0,0 +1,24 @@ +//## 2.6 Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'LOAD']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'width']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'STORE']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]']}, + {bits: 3, name: 'funct3', attr: ['3', 'width']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 5, name: 'rs2', attr: ['5', 'src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']}, +]} +.... diff --git a/src/images/wavedrom/load_store.adoc b/src/images/wavedrom/load_store.adoc deleted file mode 100644 index f9de4d1..0000000 --- a/src/images/wavedrom/load_store.adoc +++ /dev/null @@ -1,24 +0,0 @@ -//## 2.6 Load and Store Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LOAD'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'width'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'STORE'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3}, - {bits: 3, name: 'funct3', attr: ['3', 'width'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3}, -]} -.... diff --git a/src/images/wavedrom/m-st-ext-for-int-mult.adoc b/src/images/wavedrom/m-st-ext-for-int-mult.adoc deleted file mode 100644 index 520951c..0000000 --- a/src/images/wavedrom/m-st-ext-for-int-mult.adoc +++ /dev/null @@ -1,28 +0,0 @@ -//# 8 "M" Standard Extension for Integer Multiplication and Division, Version 2.0 -//## 8.1 Multiplication Operations - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'MUL/MULH[[S]U]', 'MULW'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'multiplicand', 'multiplicand'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'multiplier', 'multiplier'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV'], type: 8}, -]} -.... - -//[wavedrom, ,] -//.... -//{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-32', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: 'MULW', type: 8}, -// {bits: 5, name: 'rs1', attr: 'multiplicand', type: 4}, -// {bits: 5, name: 'rs2', attr: 'multiplier', type: 4}, -// {bits: 7, name: 'funct7', attr: 'MULDIV', type: 8}, -//]} -//.... - - diff --git a/src/images/wavedrom/m-st-ext-for-int-mult.edn b/src/images/wavedrom/m-st-ext-for-int-mult.edn new file mode 100644 index 0000000..77a3507 --- /dev/null +++ b/src/images/wavedrom/m-st-ext-for-int-mult.edn @@ -0,0 +1,28 @@ +//# 8 "M" Standard Extension for Integer Multiplication and Division, Version 2.0 +//## 8.1 Multiplication Operations + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'MUL/MULH[[S]U]', 'MULW']}, + {bits: 5, name: 'rs1', attr: ['5', 'multiplicand', 'multiplicand']}, + {bits: 5, name: 'rs2', attr: ['5', 'multiplier', 'multiplier']}, + {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV']}, +]} +.... + +//[wavedrom, ,] +//.... +//{reg: [ +// {bits: 7, name: 'opcode', attr: 'OP-32'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: 'MULW'}, +// {bits: 5, name: 'rs1', attr: 'multiplicand'}, +// {bits: 5, name: 'rs2', attr: 'multiplier'}, +// {bits: 7, name: 'funct7', attr: 'MULDIV'}, +//]} +//.... + + diff --git a/src/images/wavedrom/mem_order.adoc b/src/images/wavedrom/mem-order.edn index 75b5ab0..c7e0ba4 100644 --- a/src/images/wavedrom/mem_order.adoc +++ b/src/images/wavedrom/mem-order.edn @@ -3,10 +3,10 @@ [wavedrom,mem-order ,] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'FENCE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, + {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'FENCE']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, {bits: 1, name: 'SW', attr: 1}, {bits: 1, name: 'SR', attr: 1}, {bits: 1, name: 'SO', attr: 1}, @@ -15,6 +15,6 @@ {bits: 1, name: 'PR', attr: 1}, {bits: 1, name: 'PO', attr: 1}, {bits: 1, name: 'PI', attr: 1}, - {bits: 4, name: 'fm', attr: ['4', 'FM'], type: 8}, + {bits: 4, name: 'fm', attr: ['4', 'FM']}, ]} .... diff --git a/src/images/wavedrom/menvcfgreg.edn b/src/images/wavedrom/menvcfgreg.edn new file mode 100644 index 0000000..5ed6fb6 --- /dev/null +++ b/src/images/wavedrom/menvcfgreg.edn @@ -0,0 +1,21 @@ +//.Machine environment configuration (`menvcfg`) register. +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'FIOM'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'LPE'}, + {bits: 1, name: 'SSE'}, + {bits: 2, name: 'CBIE'}, + {bits: 1, name: 'CBCFE'}, + {bits: 1, name: 'CBZE'}, + {bits: 24, name: 'WPRI'}, + {bits: 2, name: 'PMM'}, + {bits: 25, name: 'WPRI'}, + {bits: 1, name: 'DTE'}, + {bits: 1, name: 'CDE'}, + {bits: 1, name: 'ADUE'}, + {bits: 1, name: 'PBMTE'}, + {bits: 1, name: 'STCE'}, +], config:{lanes: 4, hspace:1024}} +.... diff --git a/src/images/wavedrom/mm-env-call.adoc b/src/images/wavedrom/mm-env-call.adoc deleted file mode 100644 index 9838230..0000000 --- a/src/images/wavedrom/mm-env-call.adoc +++ /dev/null @@ -1,13 +0,0 @@ -// - -[wavedrom, ,svg] - -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7','SYSTEM','SYSTEM'],}, - {bits: 5, name: 'rd', type: 2, attr: ['5','0','0'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','PRIV','PRIV'],}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','0','0'],}, - {bits: 12, name: 'funct12', type: 8, attr: ['12','ECALL','EBREAK',]}, -], config: {bits: 32}} -....
\ No newline at end of file diff --git a/src/images/wavedrom/mm-env-call.edn b/src/images/wavedrom/mm-env-call.edn new file mode 100644 index 0000000..703c0be --- /dev/null +++ b/src/images/wavedrom/mm-env-call.edn @@ -0,0 +1,13 @@ +// + +[wavedrom, ,svg] + +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','SYSTEM','SYSTEM'],}, + {bits: 5, name: 'rd', attr: ['5','0','0'],}, + {bits: 3, name: 'funct3', attr: ['3','PRIV','PRIV'],}, + {bits: 5, name: 'rs1', attr: ['5','0','0'],}, + {bits: 12, name: 'funct12', attr: ['12','ECALL','EBREAK',]}, +], config: {bits: 32}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/mop-r.adoc b/src/images/wavedrom/mop-r.edn index 713b37c..55347e0 100644 --- a/src/images/wavedrom/mop-r.adoc +++ b/src/images/wavedrom/mop-r.edn @@ -1,10 +1,10 @@ [wavedrom, ,svg] .... {reg:[ - { bits: 7, name: 0x73, attr: ['SYSTEM'], type: 8 }, - { bits: 5, name: 'rd', type: 2 }, + { bits: 7, name: 0x73, attr: ['SYSTEM']}, + { bits: 5, name: 'rd'}, { bits: 3, name: 0x4 }, - { bits: 5, name: 'rs1', type: 4 }, + { bits: 5, name: 'rs1'}, { bits: 2, name: 'n[1:0]' }, { bits: 4, name: 0x7 }, { bits: 2, name: 'n[3:2]' }, diff --git a/src/images/wavedrom/mop-rr.adoc b/src/images/wavedrom/mop-rr.edn index b70f854..879e372 100644 --- a/src/images/wavedrom/mop-rr.adoc +++ b/src/images/wavedrom/mop-rr.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg:[ - { bits: 7, name: 0x73, attr: ['SYSTEM'], type: 8 }, - { bits: 5, name: 'rd', type: 2 }, + { bits: 7, name: 0x73, attr: ['SYSTEM']}, + { bits: 5, name: 'rd'}, { bits: 3, name: 0x4 }, - { bits: 5, name: 'rs1', type: 4 }, - { bits: 5, name: 'rs2', type: 4 }, + { bits: 5, name: 'rs1'}, + { bits: 5, name: 'rs2'}, { bits: 1, name: 0x1 }, { bits: 2, name: 'n[1:0]' }, { bits: 2, name: 0x0 }, diff --git a/src/images/wavedrom/mseccfg.edn b/src/images/wavedrom/mseccfg.edn new file mode 100644 index 0000000..82242ca --- /dev/null +++ b/src/images/wavedrom/mseccfg.edn @@ -0,0 +1,14 @@ +//.Machine security configuration (`mseccfg`) register. +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'MML'}, + {bits: 1, name: 'MMWP'}, + {bits: 1, name: 'RLB'}, + {bits: 5, name: 'WPRI'}, + {bits: 1, name: 'USEED'}, + {bits: 1, name: 'SSEED'}, + {bits: 1, name: 'MLPE'}, + {bits: 53, name: 'WPRI'}, +], config:{lanes: 4, hspace:1024}} +.... diff --git a/src/images/wavedrom/mstatushreg.edn b/src/images/wavedrom/mstatushreg.edn new file mode 100644 index 0000000..702ea11 --- /dev/null +++ b/src/images/wavedrom/mstatushreg.edn @@ -0,0 +1,15 @@ +//.Additional machine-mode status (`mstatush`) register for RV32. +[wavedrom, ,svg] +.... +{reg: [ + {bits: 4, name: 'WPRI'}, + {bits: 1, name: 'SBE'}, + {bits: 1, name: 'MBE'}, + {bits: 1, name: 'GVA'}, + {bits: 1, name: 'MPV'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MPELP'}, + {bits: 1, name: 'MDT'}, + {bits: 21, name: 'WPRI'}, +], config:{lanes: 2, hspace:1024}} +.... diff --git a/src/images/wavedrom/mstatusreg-rv321.edn b/src/images/wavedrom/mstatusreg-rv321.edn new file mode 100644 index 0000000..cc77fc2 --- /dev/null +++ b/src/images/wavedrom/mstatusreg-rv321.edn @@ -0,0 +1,29 @@ +//.Machine-mode status (`mstatus`) register for RV32 +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SPIE'}, + {bits: 1, name: 'UBE'}, + {bits: 1, name: 'MPIE'}, + {bits: 1, name: 'SPP'}, + {bits: 2, name: 'VS[1:0]'}, + {bits: 2, name: 'MPP[1:0]'}, + {bits: 2, name: 'FS[1:0]'}, + {bits: 2, name: 'XS[1:0]'}, + {bits: 1, name: 'MPRV'}, + {bits: 1, name: 'SUM'}, + {bits: 1, name: 'MXR'}, + {bits: 1, name: 'TVM'}, + {bits: 1, name: 'TW'}, + {bits: 1, name: 'TSR'}, + {bits: 1, name: 'SPELP'}, + {bits: 1, name: 'SDT'}, + {bits: 6, name: 'WPRI'}, + {bits: 1, name: 'SD'}, +], config:{lanes: 2, hspace:1024}} +.... diff --git a/src/images/wavedrom/mstatusreg.edn b/src/images/wavedrom/mstatusreg.edn new file mode 100644 index 0000000..db24626 --- /dev/null +++ b/src/images/wavedrom/mstatusreg.edn @@ -0,0 +1,39 @@ +//.Machine-mode status (`mstatus`) register for RV64 +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SPIE'}, + {bits: 1, name: 'UBE'}, + {bits: 1, name: 'MPIE'}, + {bits: 1, name: 'SPP'}, + {bits: 2, name: 'VS[1:0]'}, + {bits: 2, name: 'MPP[1:0]'}, + {bits: 2, name: 'FS[1:0]'}, + {bits: 2, name: 'XS[1:0]'}, + {bits: 1, name: 'MPRV'}, + {bits: 1, name: 'SUM'}, + {bits: 1, name: 'MXR'}, + {bits: 1, name: 'TVM'}, + {bits: 1, name: 'TW'}, + {bits: 1, name: 'TSR'}, + {bits: 1, name: 'SPELP'}, + {bits: 1, name: 'SDT'}, + {bits: 7, name: 'WPRI'}, + {bits: 2, name: 'UXL[1:0]'}, + {bits: 2, name: 'SXL[1:0]'}, + {bits: 1, name: 'SBE'}, + {bits: 1, name: 'MBE'}, + {bits: 1, name: 'GVA'}, + {bits: 1, name: 'MPV'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MPELP'}, + {bits: 1, name: 'MDT'}, + {bits: 20, name: 'WPRI'}, + {bits: 1, name: 'SD'}, +], config:{lanes: 4, hspace:1024}} +.... diff --git a/src/images/wavedrom/nop-v.adoc b/src/images/wavedrom/nop-v.adoc deleted file mode 100644 index 0c990e4..0000000 --- a/src/images/wavedrom/nop-v.adoc +++ /dev/null @@ -1,29 +0,0 @@ -//# NOP-V - -The RISC-V [User-Level ISA Specification](https://riscv.org/specifications/) defines NOP instruction as follows: - -* The NOP instruction does not change any user-visible state, except for advancing the pc. -* NOP is encoded as \`ADDI x0, x0, 0\`. - -[wavedrom, , ] ----- -{reg:[ - {name: 'opcode', bits: 7, attr: 0b0010011}, - {name: 'rd', bits: 5, attr: 0}, - {name: 'funct3', bits: 3, attr: 0}, - {name: 'rs1', bits: 5, attr: 0}, - {name: 'imm', bits: 12, attr: 0} -], config: {hspace: width}} ----- - - -NOTE: NOPs can be used to align code segments to microarchitecturally significant address boundaries, or to leave space for inline code modifications. Although **there are many possible ways** to encode a NOP, we define a canonical NOP encoding to allow microarchitectural optimizations as well as for more readable disassembly output. - -How many other possible ways to encode NOP? ----- -rd = 0 ----- - -Any Integer Computational instruction writing into \`x0\` is NOP. - -` diff --git a/src/images/wavedrom/nop.adoc b/src/images/wavedrom/nop.adoc deleted file mode 100644 index 34ad70e..0000000 --- a/src/images/wavedrom/nop.adoc +++ /dev/null @@ -1,11 +0,0 @@ -//### NOP Instruction -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'ADDI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', '0'], type: 3} -]} -.... diff --git a/src/images/wavedrom/nop.edn b/src/images/wavedrom/nop.edn new file mode 100644 index 0000000..b566909 --- /dev/null +++ b/src/images/wavedrom/nop.edn @@ -0,0 +1,11 @@ +//### NOP Instruction +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'ADDI']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', '0']} +]} +.... diff --git a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc deleted file mode 100644 index ba4e224..0000000 --- a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//quad-cnvrt-intch-xqqx - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3', 'J[N]/JX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FSGNJ'], type: 8}, -]} -.... - diff --git a/src/images/wavedrom/quad-cnvrt-intch-xqqx.edn b/src/images/wavedrom/quad-cnvrt-intch-xqqx.edn new file mode 100644 index 0000000..a388033 --- /dev/null +++ b/src/images/wavedrom/quad-cnvrt-intch-xqqx.edn @@ -0,0 +1,15 @@ +//quad-cnvrt-intch-xqqx + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3', 'J[N]/JX']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, +]} +.... + diff --git a/src/images/wavedrom/quad-cnvrt-mv.adoc b/src/images/wavedrom/quad-cnvrt-mv.adoc deleted file mode 100644 index 3fc9f86..0000000 --- a/src/images/wavedrom/quad-cnvrt-mv.adoc +++ /dev/null @@ -1,28 +0,0 @@ -//## 14.3 Quad-Precision Convert and Move Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]', 'W[U]/L[U]'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','Q','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.int.Q','FCVT.Q.int'], type: 8}, -]} -.... - -//[wavedrom, ,] -//.... -//{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'rm', attr: 'RM', type: 8}, -// {bits: 5, name: 'rs1', attr: 'src', type: 4}, -// {bits: 5, name: 'rs2', attr: ['W', 'WU', 'L', 'LU'], type: 4}, -// {bits: 2, name: 'fmt', attr: 'Q', type: 8}, -// {bits: 5, name: 'funct5', attr: 'FCVT.Q.int', type: 8}, -//]} -//.... - diff --git a/src/images/wavedrom/quad-cnvrt-mv.edn b/src/images/wavedrom/quad-cnvrt-mv.edn new file mode 100644 index 0000000..840118d --- /dev/null +++ b/src/images/wavedrom/quad-cnvrt-mv.edn @@ -0,0 +1,28 @@ +//## 14.3 Quad-Precision Convert and Move Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]', 'W[U]/L[U]']}, + {bits: 2, name: 'fmt', attr: ['2','Q','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.int.Q','FCVT.Q.int']}, +]} +.... + +//[wavedrom, ,] +//.... +//{reg: [ +// {bits: 7, name: 'opcode', attr: 'OP-FP'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'rm', attr: 'RM'}, +// {bits: 5, name: 'rs1', attr: 'src'}, +// {bits: 5, name: 'rs2', attr: ['W', 'WU', 'L', 'LU']}, +// {bits: 2, name: 'fmt', attr: 'Q'}, +// {bits: 5, name: 'funct5', attr: 'FCVT.Q.int'}, +//]} +//.... + diff --git a/src/images/wavedrom/quad-cnvt-interchange.adoc b/src/images/wavedrom/quad-cnvt-interchange.adoc deleted file mode 100644 index 1178397..0000000 --- a/src/images/wavedrom/quad-cnvt-interchange.adoc +++ /dev/null @@ -1,16 +0,0 @@ -//14 conv-mv - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-FP', 'OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','Q', 'S', 'Q', 'D'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S','Q', 'D', 'Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.S.Q', 'FCVT.Q.S', 'FCVT.D.Q', 'FCVT.Q.D'], type: 8}, -]} -.... - - diff --git a/src/images/wavedrom/quad-cnvt-interchange.edn b/src/images/wavedrom/quad-cnvt-interchange.edn new file mode 100644 index 0000000..54adc1f --- /dev/null +++ b/src/images/wavedrom/quad-cnvt-interchange.edn @@ -0,0 +1,16 @@ +//14 conv-mv + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP-FP', 'OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src','src','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','Q', 'S', 'Q', 'D']}, + {bits: 2, name: 'fmt', attr: ['2','S','Q', 'D', 'Q']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.S.Q', 'FCVT.Q.S', 'FCVT.D.Q', 'FCVT.Q.D']}, +]} +.... + + diff --git a/src/images/wavedrom/quad-compute.adoc b/src/images/wavedrom/quad-compute.adoc deleted file mode 100644 index 6aa3953..0000000 --- a/src/images/wavedrom/quad-compute.adoc +++ /dev/null @@ -1,54 +0,0 @@ -//## 14.2 Quad-Precision Computational Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','Q','Q','Q','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT'], type: 8}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','Q'], type: 8}, - {bits: 5, name: 'rs3', attr: ['5','src3'], type: 8}, -]} -.... - -//[wavedrom, ,] -//.... -//{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: ['MIN', 'MAX'], type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 2, name: 'fmt', attr: 'Q', type: 8}, -// {bits: 5, name: 'funct5', attr: 'FMIN-MAX', type: 8}, -//]} -//.... - - -//[wavedrom, ,] -//.... -//{reg: [ -// {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: 'RM', type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 2, name: 'fmt', attr: 'Q', type: 8}, -// {bits: 5, name: 'rs3', attr: 'src3', type: 4}, -//]} -//....
\ No newline at end of file diff --git a/src/images/wavedrom/quad-compute.edn b/src/images/wavedrom/quad-compute.edn new file mode 100644 index 0000000..2451ac9 --- /dev/null +++ b/src/images/wavedrom/quad-compute.edn @@ -0,0 +1,54 @@ +//## 14.2 Quad-Precision Computational Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src']}, + {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0']}, + {bits: 2, name: 'fmt', attr: ['2','Q','Q','Q','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','Q']}, + {bits: 5, name: 'rs3', attr: ['5','src3']}, +]} +.... + +//[wavedrom, ,] +//.... +//{reg: [ +// {bits: 7, name: 'opcode', attr: 'OP-FP'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: ['MIN', 'MAX']}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 2, name: 'fmt', attr: 'Q'}, +// {bits: 5, name: 'funct5', attr: 'FMIN-MAX'}, +//]} +//.... + + +//[wavedrom, ,] +//.... +//{reg: [ +// {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']}, +// {bits: 5, name: 'rd', attr: 'dest'} +// {bits: 3, name: 'funct3', attr: 'RM'}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 2, name: 'fmt', attr: 'Q'}, +// {bits: 5, name: 'rs3', attr: 'src3'}, +//]} +//....
\ No newline at end of file diff --git a/src/images/wavedrom/quad-float-clssfy.adoc b/src/images/wavedrom/quad-float-clssfy.adoc deleted file mode 100644 index 0023c7d..0000000 --- a/src/images/wavedrom/quad-float-clssfy.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 14.5 Quad-Precision Floating-Point Classify Instruction - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','001'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8}, -]} -.... - diff --git a/src/images/wavedrom/quad-float-clssfy.edn b/src/images/wavedrom/quad-float-clssfy.edn new file mode 100644 index 0000000..325239e --- /dev/null +++ b/src/images/wavedrom/quad-float-clssfy.edn @@ -0,0 +1,15 @@ +//## 14.5 Quad-Precision Floating-Point Classify Instruction + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','001']}, + {bits: 5, name: 'rs1', attr: ['5','src']}, + {bits: 5, name: 'rs2', attr: ['5','0']}, + {bits: 2, name: 'fmt', attr: ['2','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, +]} +.... + diff --git a/src/images/wavedrom/quad-float-compare.adoc b/src/images/wavedrom/quad-float-compare.adoc deleted file mode 100644 index 2269bc9..0000000 --- a/src/images/wavedrom/quad-float-compare.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 14.4 Quad-Precision Floating-Point Compare Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','Q'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8}, -]} -.... - diff --git a/src/images/wavedrom/quad-float-compare.edn b/src/images/wavedrom/quad-float-compare.edn new file mode 100644 index 0000000..86e8f83 --- /dev/null +++ b/src/images/wavedrom/quad-float-compare.edn @@ -0,0 +1,15 @@ +//## 14.4 Quad-Precision Floating-Point Compare Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','Q']}, + {bits: 5, name: 'funct5', attr: ['5','FCMP']}, +]} +.... + diff --git a/src/images/wavedrom/quad-ls.adoc b/src/images/wavedrom/quad-ls.adoc deleted file mode 100644 index 3ba4099..0000000 --- a/src/images/wavedrom/quad-ls.adoc +++ /dev/null @@ -1,26 +0,0 @@ -//## 14.1 Quad-Precision Load and Store Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','LOAD-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'width', attr: ['3','Q'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'], type: 3}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','STORE-FP'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]'], type: 3}, - {bits: 3, name: 'width', attr: ['3','Q'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, -]} -.... - - diff --git a/src/images/wavedrom/quad-ls.edn b/src/images/wavedrom/quad-ls.edn new file mode 100644 index 0000000..d855534 --- /dev/null +++ b/src/images/wavedrom/quad-ls.edn @@ -0,0 +1,26 @@ +//## 14.1 Quad-Precision Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','LOAD-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'width', attr: ['3','Q']}, + {bits: 5, name: 'rs1', attr: ['5','base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]']}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','STORE-FP']}, + {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]']}, + {bits: 3, name: 'width', attr: ['3','Q']}, + {bits: 5, name: 'rs1', attr: ['5','base']}, + {bits: 5, name: 'rs2', attr: ['5','src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]']}, +]} +.... + + diff --git a/src/images/wavedrom/reg-based-ldnstr.adoc b/src/images/wavedrom/reg-based-ldnstr.edn index ea9e245..031ea1a 100644 --- a/src/images/wavedrom/reg-based-ldnstr.adoc +++ b/src/images/wavedrom/reg-based-ldnstr.edn @@ -4,12 +4,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 2, name: 'op', attr: ['2', 'C0', 'C0', 'C0', 'C0', 'C0'], type: 8}, - {bits: 3, name: 'rdʹ', attr: ['3', 'dest', 'dest','dest','dest','dest'], type: 3}, - {bits: 2, name: 'imm', attr:['2', 'offset[2|6]', 'offset[7:6]', 'offset[7:6]', 'offset[2|6]', 'offset[7:6]'], type: 2}, - {bits: 3, name: 'rs1ʹ', attr: ['3', 'base', 'base', 'base', 'base', 'base'], type: 2}, - {bits: 3, name: 'imm', attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]'], type: 3}, - {bits: 3, name: 'funct3', attr: ['3', 'C.LW', 'C.LD', 'C.LQ', 'C.FLW', 'C.FLD'], type: 8}, + {bits: 2, name: 'op', attr: ['2', 'C0', 'C0', 'C0', 'C0', 'C0']}, + {bits: 3, name: 'rdʹ', attr: ['3', 'dest', 'dest','dest','dest','dest']}, + {bits: 2, name: 'imm', attr:['2', 'offset[2|6]', 'offset[7:6]', 'offset[7:6]', 'offset[2|6]', 'offset[7:6]']}, + {bits: 3, name: 'rs1ʹ', attr: ['3', 'base', 'base', 'base', 'base', 'base']}, + {bits: 3, name: 'imm', attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]']}, + {bits: 3, name: 'funct3', attr: ['3', 'C.LW', 'C.LD', 'C.LQ', 'C.FLW', 'C.FLD']}, ], config: {bits: 16}} .... diff --git a/src/images/wavedrom/rv64-lui-auipc.edn b/src/images/wavedrom/rv64-lui-auipc.edn new file mode 100644 index 0000000..5850133 --- /dev/null +++ b/src/images/wavedrom/rv64-lui-auipc.edn @@ -0,0 +1,10 @@ +//lui-auipc + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, + {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]']} +]} +.... diff --git a/src/images/wavedrom/rv64_lui-auipc.adoc b/src/images/wavedrom/rv64_lui-auipc.adoc deleted file mode 100644 index 132c770..0000000 --- a/src/images/wavedrom/rv64_lui-auipc.adoc +++ /dev/null @@ -1,10 +0,0 @@ -//lui-auipc - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest'], type: 2}, - {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]'], type: 3} -]} -.... diff --git a/src/images/wavedrom/rv64i-base-int.adoc b/src/images/wavedrom/rv64i-base-int.adoc deleted file mode 100644 index e4edaf3..0000000 --- a/src/images/wavedrom/rv64i-base-int.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//# 6 RV64I Base Integer Instruction Set, Version 2.1 -//## 6.2 Integer Computational Instructions -//### Integer Register-Immediate Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'ADDIW'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]'], type: 3} -]} -.... - diff --git a/src/images/wavedrom/rv64i-base-int.edn b/src/images/wavedrom/rv64i-base-int.edn new file mode 100644 index 0000000..4ff3b83 --- /dev/null +++ b/src/images/wavedrom/rv64i-base-int.edn @@ -0,0 +1,15 @@ +//# 6 RV64I Base Integer Instruction Set, Version 2.1 +//## 6.2 Integer Computational Instructions +//### Integer Register-Immediate Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'ADDIW']}, + {bits: 5, name: 'rs1', attr: ['5', 'src']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]']} +]} +.... + diff --git a/src/images/wavedrom/rv64i-int-reg-reg.edn b/src/images/wavedrom/rv64i-int-reg-reg.edn new file mode 100644 index 0000000..6d29ec7 --- /dev/null +++ b/src/images/wavedrom/rv64i-int-reg-reg.edn @@ -0,0 +1,27 @@ + +//rv64i int-reg-reg +//### Integer Register-Register Operations + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP-32', 'OP-32', 'OP-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'SLL/SRL', 'SRA', 'ADDW', 'SLLW/SRLW', 'SUBW/SRAW']}, + {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1', 'src1']}, + {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2', 'src2']}, + {bits: 7, name: 'funct7', attr: ['7', '0000000', '0100000', '0000000', '0000000', '0100000']} +]} +.... + +//[wavedrom, ,svg] +//.... +//{reg: [ +// {bits: 7, name: 'opcode', attr: 'OP-32'}, +// {bits: 5, name: 'rd', attr: 'dest'}, +// {bits: 3, name: 'funct3', attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']}, +// {bits: 5, name: 'rs1', attr: 'src1'}, +// {bits: 5, name: 'rs2', attr: 'src2'}, +// {bits: 7, name: 'funct7', attr: [0, 0, 0, 32, 32]} +//]} +//.... diff --git a/src/images/wavedrom/rv64i-slli.adoc b/src/images/wavedrom/rv64i-slli.edn index 038a052..b261564 100644 --- a/src/images/wavedrom/rv64i-slli.adoc +++ b/src/images/wavedrom/rv64i-slli.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src'], type: 4}, - {bits: 6, name: 'imm[5:0]', attr: ['6', 'shamt[5:0]', 'shamt[5:0]', 'shamt[5:0]'], type: 3}, - {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000'], type: 8} + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI']}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']}, + {bits: 6, name: 'imm[5:0]', attr: ['6', 'shamt[5:0]', 'shamt[5:0]', 'shamt[5:0]']}, + {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000']} ]} .... diff --git a/src/images/wavedrom/rv64i-slliw.adoc b/src/images/wavedrom/rv64i-slliw.edn index bd51e9b..0ca01ba 100644 --- a/src/images/wavedrom/rv64i-slliw.adoc +++ b/src/images/wavedrom/rv64i-slliw.edn @@ -1,12 +1,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'SLLIW', 'SRLIW', 'SRAIW'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src'], type: 4}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]'], type: 3}, - {bits: 1, name: '[5]', attr: ['1', '0', '0', '0'], type: 3}, - {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000'], type: 8} + {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32']}, + {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']}, + {bits: 3, name: 'funct3', attr: ['3', 'SLLIW', 'SRLIW', 'SRAIW']}, + {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]']}, + {bits: 1, name: '[5]', attr: ['1', '0', '0', '0']}, + {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000']} ]} .... diff --git a/src/images/wavedrom/rv64i_int-reg-reg.adoc b/src/images/wavedrom/rv64i_int-reg-reg.adoc deleted file mode 100644 index a69e718..0000000 --- a/src/images/wavedrom/rv64i_int-reg-reg.adoc +++ /dev/null @@ -1,27 +0,0 @@ - -//rv64i int-reg-reg -//### Integer Register-Register Operations - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP-32', 'OP-32', 'OP-32'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'SLL/SRL', 'SRA', 'ADDW', 'SLLW/SRLW', 'SUBW/SRAW'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1', 'src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2', 'src2'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', '000000', '010000', '000000', '000000', '010000'], type: 8} -]} -.... - -//[wavedrom, ,svg] -//.... -//{reg: [ -// {bits: 7, name: 'opcode', attr: 'OP-32', type: 8}, -// {bits: 5, name: 'rd', attr: 'dest', type: 2}, -// {bits: 3, name: 'funct3', attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW'], type: 8}, -// {bits: 5, name: 'rs1', attr: 'src1', type: 4}, -// {bits: 5, name: 'rs2', attr: 'src2', type: 4}, -// {bits: 7, name: 'funct7', attr: [0, 0, 0, 32, 32], type: 8} -//]} -//.... diff --git a/src/images/wavedrom/s-immediate.edn b/src/images/wavedrom/s-immediate.edn new file mode 100644 index 0000000..324b4a3 --- /dev/null +++ b/src/images/wavedrom/s-immediate.edn @@ -0,0 +1,11 @@ +//#### S-immediate + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: '[7]'}, + {bits: 4, name: 'inst[11:8]'}, + {bits: 6, name: 'inst[30:25]'}, + {bits: 21, name: '— inst[31] —'}, +], config:{fontsize: 12, label:{right: 'S-immediate'}}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/sfenceinvalir.edn b/src/images/wavedrom/sfenceinvalir.edn index 639be34..747df40 100644 --- a/src/images/wavedrom/sfenceinvalir.edn +++ b/src/images/wavedrom/sfenceinvalir.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', '1'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.INVAL.IR'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, + {bits: 5, name: 'rs2', attr: ['5', '1']}, + {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.INVAL.IR']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/sfencevma.edn b/src/images/wavedrom/sfencevma.edn index a7a7663..e06d949 100644 --- a/src/images/wavedrom/sfencevma.edn +++ b/src/images/wavedrom/sfencevma.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'vaddr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'asid'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.VMA'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', 'vaddr']}, + {bits: 5, name: 'rs2', attr: ['5', 'asid']}, + {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.VMA']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/sfencewinval.edn b/src/images/wavedrom/sfencewinval.edn index 2973af8..712f1c1 100644 --- a/src/images/wavedrom/sfencewinval.edn +++ b/src/images/wavedrom/sfencewinval.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', '0'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.W.INVAL'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, + {bits: 5, name: 'rs2', attr: ['5', '0']}, + {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.W.INVAL']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/sinvalvma.edn b/src/images/wavedrom/sinvalvma.edn index 89d0d40..1752a52 100644 --- a/src/images/wavedrom/sinvalvma.edn +++ b/src/images/wavedrom/sinvalvma.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'PRIV'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'vaddr'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'asid'], type: 4}, - {bits: 7, name: 'funct7', attr: ['7', 'SINVAL.VMA'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, + {bits: 5, name: 'rs1', attr: ['5', 'vaddr']}, + {bits: 5, name: 'rs2', attr: ['5', 'asid']}, + {bits: 7, name: 'funct7', attr: ['7', 'SINVAL.VMA']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/sp-load-store-2.adoc b/src/images/wavedrom/sp-load-store-2.adoc deleted file mode 100644 index f1025e9..0000000 --- a/src/images/wavedrom/sp-load-store-2.adoc +++ /dev/null @@ -1,24 +0,0 @@ -//## 12.5 Single-Precision Load and Store Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'width', attr: ['3', 'W'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3}, - {bits: 3, name: 'width', attr: ['3', 'W'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/sp-load-store-2.edn b/src/images/wavedrom/sp-load-store-2.edn new file mode 100644 index 0000000..a95b861 --- /dev/null +++ b/src/images/wavedrom/sp-load-store-2.edn @@ -0,0 +1,24 @@ +//## 12.5 Single-Precision Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'width', attr: ['3', 'W']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]']}, + {bits: 3, name: 'width', attr: ['3', 'W']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 5, name: 'rs2', attr: ['5', 'src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/sp-load-store.adoc b/src/images/wavedrom/sp-load-store.adoc deleted file mode 100644 index 192626b..0000000 --- a/src/images/wavedrom/sp-load-store.adoc +++ /dev/null @@ -1,25 +0,0 @@ -//## 12.5 Single-Precision Load and Store Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'width', attr: ['3', 'H'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3}, -]} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP'], type: 8}, - {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3}, - {bits: 3, name: 'width', attr: ['3', 'H'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', 'base'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5', 'src'], type: 4}, - {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3}, -]} -.... - diff --git a/src/images/wavedrom/sp-load-store.edn b/src/images/wavedrom/sp-load-store.edn new file mode 100644 index 0000000..6b1fe49 --- /dev/null +++ b/src/images/wavedrom/sp-load-store.edn @@ -0,0 +1,25 @@ +//## 12.5 Single-Precision Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'width', attr: ['3', 'H']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP']}, + {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]']}, + {bits: 3, name: 'width', attr: ['3', 'H']}, + {bits: 5, name: 'rs1', attr: ['5', 'base']}, + {bits: 5, name: 'rs2', attr: ['5', 'src']}, + {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']}, +]} +.... + diff --git a/src/images/wavedrom/spfloat-classify.adoc b/src/images/wavedrom/spfloat-classify.adoc deleted file mode 100644 index 236880d..0000000 --- a/src/images/wavedrom/spfloat-classify.adoc +++ /dev/null @@ -1,14 +0,0 @@ -//## 12.9 Single-Precision Floating-Point Classify Instruction - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','001'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0'], type: 8}, - {bits: 2, name: 'fmt', attr: ['2','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8}, -]} -.... diff --git a/src/images/wavedrom/spfloat-classify.edn b/src/images/wavedrom/spfloat-classify.edn new file mode 100644 index 0000000..52ec8bc --- /dev/null +++ b/src/images/wavedrom/spfloat-classify.edn @@ -0,0 +1,14 @@ +//## 12.9 Single-Precision Floating-Point Classify Instruction + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','001']}, + {bits: 5, name: 'rs1', attr: ['5','src']}, + {bits: 5, name: 'rs2', attr: ['5','0']}, + {bits: 2, name: 'fmt', attr: ['2','S']}, + {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, +]} +.... diff --git a/src/images/wavedrom/spfloat-cn-cmp.adoc b/src/images/wavedrom/spfloat-cn-cmp.adoc deleted file mode 100644 index e46a099..0000000 --- a/src/images/wavedrom/spfloat-cn-cmp.adoc +++ /dev/null @@ -1,16 +0,0 @@ -//sp float convert and compare - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP', 'OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest', 'dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src', 'src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]D', 'W[U]/L[U]'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCVT.int.fmt', 'FCVT.fmt.int'], type: 8}, -]} -.... - - diff --git a/src/images/wavedrom/spfloat-cn-cmp.edn b/src/images/wavedrom/spfloat-cn-cmp.edn new file mode 100644 index 0000000..0e5db87 --- /dev/null +++ b/src/images/wavedrom/spfloat-cn-cmp.edn @@ -0,0 +1,16 @@ +//sp float convert and compare + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP', 'OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest', 'dest']}, + {bits: 3, name: 'rm', attr: ['3','RM','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src', 'src']}, + {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]D', 'W[U]/L[U]']}, + {bits: 2, name: 'fmt', attr: ['2','S','S']}, + {bits: 5, name: 'funct5', attr: ['5','FCVT.int.fmt', 'FCVT.fmt.int']}, +]} +.... + + diff --git a/src/images/wavedrom/spfloat-comp.adoc b/src/images/wavedrom/spfloat-comp.adoc deleted file mode 100644 index 7059e8e..0000000 --- a/src/images/wavedrom/spfloat-comp.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//## 12.8 Single-Precision Floating-Point Compare Instructions - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','EQ', 'LT', 'LE'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8}, -]} -.... - diff --git a/src/images/wavedrom/spfloat-comp.edn b/src/images/wavedrom/spfloat-comp.edn new file mode 100644 index 0000000..05012a7 --- /dev/null +++ b/src/images/wavedrom/spfloat-comp.edn @@ -0,0 +1,15 @@ +//## 12.8 Single-Precision Floating-Point Compare Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','EQ', 'LT', 'LE']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','S']}, + {bits: 5, name: 'funct5', attr: ['5','FCMP']}, +]} +.... + diff --git a/src/images/wavedrom/spfloat-mv.adoc b/src/images/wavedrom/spfloat-mv.adoc deleted file mode 100644 index d5df81d..0000000 --- a/src/images/wavedrom/spfloat-mv.adoc +++ /dev/null @@ -1,15 +0,0 @@ -//SP flating point move - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','000', '000'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src','src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','0','0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FMV.X.W','FMV.W.X'], type: 8}, -]} -.... - diff --git a/src/images/wavedrom/spfloat-mv.edn b/src/images/wavedrom/spfloat-mv.edn new file mode 100644 index 0000000..47a63ee --- /dev/null +++ b/src/images/wavedrom/spfloat-mv.edn @@ -0,0 +1,15 @@ +//SP flating point move + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','000', '000']}, + {bits: 5, name: 'rs1', attr: ['5','src','src']}, + {bits: 5, name: 'rs2', attr: ['5','0','0']}, + {bits: 2, name: 'fmt', attr: ['2','S','S']}, + {bits: 5, name: 'funct5', attr: ['5','FMV.X.W','FMV.W.X']}, +]} +.... + diff --git a/src/images/wavedrom/spfloat-sign-inj.adoc b/src/images/wavedrom/spfloat-sign-inj.adoc deleted file mode 100644 index 74040b7..0000000 --- a/src/images/wavedrom/spfloat-sign-inj.adoc +++ /dev/null @@ -1,14 +0,0 @@ -//sp float sign injection - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', 'dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','J[N]/JX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5','FSGNJ'], type: 8}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/spfloat-sign-inj.edn b/src/images/wavedrom/spfloat-sign-inj.edn new file mode 100644 index 0000000..8c81976 --- /dev/null +++ b/src/images/wavedrom/spfloat-sign-inj.edn @@ -0,0 +1,14 @@ +//sp float sign injection + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5', 'dest']}, + {bits: 3, name: 'rm', attr: ['3','J[N]/JX']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','S']}, + {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/spfloat-zfh.adoc b/src/images/wavedrom/spfloat-zfh.edn index d53e6bd..4221c2d 100644 --- a/src/images/wavedrom/spfloat-zfh.adoc +++ b/src/images/wavedrom/spfloat-zfh.edn @@ -3,12 +3,12 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'MIN/MAX', 'RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src1', 'src'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', 'src2', '0'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H', 'H', 'H', 'H'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'MIN/MAX', 'RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src1', 'src']}, + {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', 'src2', '0']}, + {bits: 2, name: 'fmt', attr: ['2','H', 'H', 'H', 'H']}, + {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']}, ]} ....
\ No newline at end of file diff --git a/src/images/wavedrom/spfloat.adoc b/src/images/wavedrom/spfloat.edn index 9384544..97679bd 100644 --- a/src/images/wavedrom/spfloat.adoc +++ b/src/images/wavedrom/spfloat.edn @@ -3,13 +3,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'RM','MIN/MAX'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src', 'src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', '0', 'src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S', 'S', 'S', 'S'], type: 8}, - {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FSQRT','FMIN-MAX'], type: 8}, + {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, + {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'RM','MIN/MAX']}, + {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src', 'src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', '0', 'src2']}, + {bits: 2, name: 'fmt', attr: ['2','S', 'S', 'S', 'S']}, + {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FSQRT','FMIN-MAX']}, ]} .... diff --git a/src/images/wavedrom/spfloat2-zfh.adoc b/src/images/wavedrom/spfloat2-zfh.adoc deleted file mode 100644 index 44789da..0000000 --- a/src/images/wavedrom/spfloat2-zfh.adoc +++ /dev/null @@ -1,12 +0,0 @@ -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','H'], type: 8}, - {bits: 5, name: 'rs3', attr: ['5','src3'], type: 4}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/spfloat2-zfh.edn b/src/images/wavedrom/spfloat2-zfh.edn new file mode 100644 index 0000000..64d3fa7 --- /dev/null +++ b/src/images/wavedrom/spfloat2-zfh.edn @@ -0,0 +1,12 @@ +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','H']}, + {bits: 5, name: 'rs3', attr: ['5','src3']}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/spfloat2.adoc b/src/images/wavedrom/spfloat2.adoc deleted file mode 100644 index 8c2b976..0000000 --- a/src/images/wavedrom/spfloat2.adoc +++ /dev/null @@ -1,12 +0,0 @@ -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8}, - {bits: 5, name: 'rd', attr: ['5','dest'], type: 2}, - {bits: 3, name: 'rm', attr: ['3','RM'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5','src1'], type: 4}, - {bits: 5, name: 'rs2', attr: ['5','src2'], type: 4}, - {bits: 2, name: 'fmt', attr: ['2','S'], type: 8}, - {bits: 5, name: 'rs3', attr: ['5','src3'], type: 4}, -]} -....
\ No newline at end of file diff --git a/src/images/wavedrom/spfloat2.edn b/src/images/wavedrom/spfloat2.edn new file mode 100644 index 0000000..cee5bdc --- /dev/null +++ b/src/images/wavedrom/spfloat2.edn @@ -0,0 +1,12 @@ +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, + {bits: 5, name: 'rd', attr: ['5','dest']}, + {bits: 3, name: 'rm', attr: ['3','RM']}, + {bits: 5, name: 'rs1', attr: ['5','src1']}, + {bits: 5, name: 'rs2', attr: ['5','src2']}, + {bits: 2, name: 'fmt', attr: ['2','S']}, + {bits: 5, name: 'rs3', attr: ['5','src3']}, +]} +....
\ No newline at end of file diff --git a/src/images/wavedrom/sploat2.adoc b/src/images/wavedrom/sploat2.adoc deleted file mode 100644 index e69de29..0000000 --- a/src/images/wavedrom/sploat2.adoc +++ /dev/null diff --git a/src/images/wavedrom/transformedatomicinst.edn b/src/images/wavedrom/transformedatomicinst.edn index d598bc3..ab4f989 100644 --- a/src/images/wavedrom/transformedatomicinst.edn +++ b/src/images/wavedrom/transformedatomicinst.edn @@ -1,13 +1,13 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7']}, - {bits: 5, name: 'rd', type: 2, attr: ['5']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3']}, - {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']}, - {bits: 5, name: 'rs2',type: 4, attr: ['5']}, - {bits: 1, name: 'rl',type: 4, attr: ['1']}, - {bits: 1, name: 'aq',type: 4, attr: ['1']}, - {bits: 5, name: 'funct5', type: 8, attr: ['5']}, + {bits: 7, name: 'opcode', attr: ['7']}, + {bits: 5, name: 'rd', attr: ['5']}, + {bits: 3, name: 'funct3', attr: ['3']}, + {bits: 5, name: 'Addr. Offset', attr: ['5']}, + {bits: 5, name: 'rs2', attr: ['5']}, + {bits: 1, name: 'rl', attr: ['1']}, + {bits: 1, name: 'aq', attr: ['1']}, + {bits: 5, name: 'funct5', attr: ['5']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/transformedloadinst.edn b/src/images/wavedrom/transformedloadinst.edn index 0d6e5ab..3d14134 100644 --- a/src/images/wavedrom/transformedloadinst.edn +++ b/src/images/wavedrom/transformedloadinst.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7']}, - {bits: 5, name: 'rd', type: 2, attr: ['5']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3']}, - {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']}, - {bits: 5, name: '0', type: 4, attr: ['5']}, - {bits: 7, name: '0', type: 8, attr: ['7']}, + {bits: 7, name: 'opcode', attr: ['7']}, + {bits: 5, name: 'rd', attr: ['5']}, + {bits: 3, name: 'funct3', attr: ['3']}, + {bits: 5, name: 'Addr. Offset', attr: ['5']}, + {bits: 5, name: '0', attr: ['5']}, + {bits: 7, name: '0', attr: ['7']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/transformedstoreinst.edn b/src/images/wavedrom/transformedstoreinst.edn index e807ad5..789a6e4 100644 --- a/src/images/wavedrom/transformedstoreinst.edn +++ b/src/images/wavedrom/transformedstoreinst.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7']}, - {bits: 5, name: '0', type: 2, attr: ['5']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3']}, - {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5']}, - {bits: 7, name: '0', type: 8, attr: ['7']}, + {bits: 7, name: 'opcode', attr: ['7']}, + {bits: 5, name: '0', attr: ['5']}, + {bits: 3, name: 'funct3', attr: ['3']}, + {bits: 5, name: 'Addr. Offset', attr: ['5']}, + {bits: 5, name: 'rs2', attr: ['5']}, + {bits: 7, name: '0', attr: ['7']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/transformedvmaccessinst.edn b/src/images/wavedrom/transformedvmaccessinst.edn index 9c7e9e3..65b6a1c 100644 --- a/src/images/wavedrom/transformedvmaccessinst.edn +++ b/src/images/wavedrom/transformedvmaccessinst.edn @@ -1,11 +1,11 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7']}, - {bits: 5, name: 'rd', type: 2, attr: ['5']}, - {bits: 3, name: 'funct3', type: 8, attr: ['3']}, - {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']}, - {bits: 5, name: 'rs2', type: 4, attr: ['5']}, - {bits: 7, name: 'funct7', type: 8, attr: ['7']}, + {bits: 7, name: 'opcode', attr: ['7']}, + {bits: 5, name: 'rd', attr: ['5']}, + {bits: 3, name: 'funct3', attr: ['3']}, + {bits: 5, name: 'Addr. Offset', attr: ['5']}, + {bits: 5, name: 'rs2', attr: ['5']}, + {bits: 7, name: 'funct7', attr: ['7']}, ], config: {bits: 32}} ....
\ No newline at end of file diff --git a/src/images/wavedrom/trap-return.adoc b/src/images/wavedrom/trap-return.adoc deleted file mode 100644 index 1e15e2b..0000000 --- a/src/images/wavedrom/trap-return.adoc +++ /dev/null @@ -1,13 +0,0 @@ -// - -[wavedrom, ,svg] - -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7','SYSTEM'],}, - {bits: 5, name: 'rd', type: 2, attr: ['5','0'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','PRIV'],}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','0'],}, - {bits: 12, name: 'funct12', type: 8, attr: ['12','MRET/SRET',]}, -], config: {bits: 32}} -....
\ No newline at end of file diff --git a/src/images/wavedrom/trap-return.edn b/src/images/wavedrom/trap-return.edn new file mode 100644 index 0000000..7467ad6 --- /dev/null +++ b/src/images/wavedrom/trap-return.edn @@ -0,0 +1,13 @@ +// + +[wavedrom, ,svg] + +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','SYSTEM'],}, + {bits: 5, name: 'rd', attr: ['5','0'],}, + {bits: 3, name: 'funct3', attr: ['3','PRIV'],}, + {bits: 5, name: 'rs1', attr: ['5','0'],}, + {bits: 12, name: 'funct12', attr: ['12','MRET/SRET',]}, +], config: {bits: 32}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/u-immediate.edn b/src/images/wavedrom/u-immediate.edn new file mode 100644 index 0000000..3b8ab61 --- /dev/null +++ b/src/images/wavedrom/u-immediate.edn @@ -0,0 +1,11 @@ +//#### U-immediate + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 12, name: '0'}, + {bits: 8, name: 'inst[19:12]'}, + {bits: 11, name: 'inst[30:20]'}, + {bits: 1, name: '[31]'}, +], config:{fontsize: 12, label:{right: 'U-immediate'}}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/v-inst-table.adoc b/src/images/wavedrom/v-inst-table.edn index 0c02220..0c02220 100644 --- a/src/images/wavedrom/v-inst-table.adoc +++ b/src/images/wavedrom/v-inst-table.edn diff --git a/src/images/wavedrom/valu-format.adoc b/src/images/wavedrom/valu-format.edn index cdd3447..95732e7 100644 --- a/src/images/wavedrom/valu-format.adoc +++ b/src/images/wavedrom/valu-format.edn @@ -16,10 +16,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPIVV'}, - {bits: 5, name: 'vd', type: 2}, + {bits: 5, name: 'vd'}, {bits: 3, name: 0}, - {bits: 5, name: 'vs1', type: 2}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'vs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -29,10 +29,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPFVV'}, - {bits: 5, name: 'vd / rd', type: 7}, + {bits: 5, name: 'vd / rd'}, {bits: 3, name: 1}, - {bits: 5, name: 'vs1', type: 2}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'vs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -42,10 +42,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPMVV'}, - {bits: 5, name: 'vd / rd', type: 7}, + {bits: 5, name: 'vd / rd'}, {bits: 3, name: 2}, - {bits: 5, name: 'vs1', type: 2}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'vs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -55,10 +55,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: ['OPIVI']}, - {bits: 5, name: 'vd', type: 2}, + {bits: 5, name: 'vd'}, {bits: 3, name: 3}, - {bits: 5, name: 'imm[4:0]', type: 5}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'imm[4:0]'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -68,10 +68,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPIVX'}, - {bits: 5, name: 'vd', type: 2}, + {bits: 5, name: 'vd'}, {bits: 3, name: 4}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -81,10 +81,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPFVF'}, - {bits: 5, name: 'vd', type: 2}, + {bits: 5, name: 'vd'}, {bits: 3, name: 5}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} @@ -94,10 +94,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'OPMVX'}, - {bits: 5, name: 'vd / rd', type: 7}, + {bits: 5, name: 'vd / rd'}, {bits: 3, name: 6}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'vs2', type: 2}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'vs2'}, {bits: 1, name: 'vm'}, {bits: 6, name: 'funct6'}, ]} diff --git a/src/images/wavedrom/vcfg-format.adoc b/src/images/wavedrom/vcfg-format.edn index ac0353c..0219e6b 100644 --- a/src/images/wavedrom/vcfg-format.adoc +++ b/src/images/wavedrom/vcfg-format.edn @@ -12,10 +12,10 @@ Formats for Vector Configuration Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'vsetvli'}, - {bits: 5, name: 'rd', type: 4}, + {bits: 5, name: 'rd'}, {bits: 3, name: 7}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 11, name: 'vtypei[10:0]', type: 5}, + {bits: 5, name: 'rs1'}, + {bits: 11, name: 'vtypei[10:0]'}, {bits: 1, name: '0'}, ]} .... @@ -24,10 +24,10 @@ Formats for Vector Configuration Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'vsetivli'}, - {bits: 5, name: 'rd', type: 4}, + {bits: 5, name: 'rd'}, {bits: 3, name: 7}, - {bits: 5, name: 'uimm[4:0]', type: 5}, - {bits: 10, name: 'vtypei[9:0]', type: 5}, + {bits: 5, name: 'uimm[4:0]'}, + {bits: 10, name: 'vtypei[9:0]'}, {bits: 1, name: '1'}, {bits: 1, name: '1'}, ]} @@ -37,10 +37,10 @@ Formats for Vector Configuration Instructions under OP-V major opcode .... {reg: [ {bits: 7, name: 0x57, attr: 'vsetvl'}, - {bits: 5, name: 'rd', type: 4}, + {bits: 5, name: 'rd'}, {bits: 3, name: 7}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'rs2', type: 4}, + {bits: 5, name: 'rs1'}, + {bits: 5, name: 'rs2'}, {bits: 6, name: 0x00}, {bits: 1, name: 1}, ]} diff --git a/src/images/wavedrom/vfrec7.adoc b/src/images/wavedrom/vfrec7.edn index d33f44e..d33f44e 100644 --- a/src/images/wavedrom/vfrec7.adoc +++ b/src/images/wavedrom/vfrec7.edn diff --git a/src/images/wavedrom/vfrsqrt7.adoc b/src/images/wavedrom/vfrsqrt7.edn index 8ebc621..8ebc621 100644 --- a/src/images/wavedrom/vfrsqrt7.adoc +++ b/src/images/wavedrom/vfrsqrt7.edn diff --git a/src/images/wavedrom/vmem-format.adoc b/src/images/wavedrom/vmem-format.edn index f9b25ee..58cc6bf 100644 --- a/src/images/wavedrom/vmem-format.adoc +++ b/src/images/wavedrom/vmem-format.edn @@ -12,9 +12,9 @@ Format for Vector Load Instructions under LOAD-FP major opcode .... {reg: [ {bits: 7, name: 0x7, attr: 'VL* unit-stride'}, - {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 5, name: 'vd', attr: 'destination of load'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'rs1', attr: 'base address'}, {bits: 5, name: 'lumop'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, @@ -27,10 +27,10 @@ Format for Vector Load Instructions under LOAD-FP major opcode .... {reg: [ {bits: 7, name: 0x7, attr: 'VLS* strided'}, - {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 5, name: 'vd', attr: 'destination of load'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, - {bits: 5, name: 'rs2', attr: 'stride', type: 4}, + {bits: 5, name: 'rs1', attr: 'base address'}, + {bits: 5, name: 'rs2', attr: 'stride'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, @@ -42,10 +42,10 @@ Format for Vector Load Instructions under LOAD-FP major opcode .... {reg: [ {bits: 7, name: 0x7, attr: 'VLX* indexed'}, - {bits: 5, name: 'vd', attr: 'destination of load', type: 2}, + {bits: 5, name: 'vd', attr: 'destination of load'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, - {bits: 5, name: 'vs2', attr: 'address offsets', type: 2}, + {bits: 5, name: 'rs1', attr: 'base address'}, + {bits: 5, name: 'vs2', attr: 'address offsets'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, @@ -66,9 +66,9 @@ Format for Vector Store Instructions under STORE-FP major opcode .... {reg: [ {bits: 7, name: 0x27, attr: 'VS* unit-stride'}, - {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 5, name: 'vs3', attr: 'store data'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, + {bits: 5, name: 'rs1', attr: 'base address'}, {bits: 5, name: 'sumop'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, @@ -81,10 +81,10 @@ Format for Vector Store Instructions under STORE-FP major opcode .... {reg: [ {bits: 7, name: 0x27, attr: 'VSS* strided'}, - {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 5, name: 'vs3', attr: 'store data'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, - {bits: 5, name: 'rs2', attr: 'stride', type: 4}, + {bits: 5, name: 'rs1', attr: 'base address'}, + {bits: 5, name: 'rs2', attr: 'stride'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, @@ -96,10 +96,10 @@ Format for Vector Store Instructions under STORE-FP major opcode .... {reg: [ {bits: 7, name: 0x27, attr: 'VSX* indexed'}, - {bits: 5, name: 'vs3', attr: 'store data', type: 2}, + {bits: 5, name: 'vs3', attr: 'store data'}, {bits: 3, name: 'width'}, - {bits: 5, name: 'rs1', attr: 'base address', type: 4}, - {bits: 5, name: 'vs2', attr: 'address offsets', type: 2}, + {bits: 5, name: 'rs1', attr: 'base address'}, + {bits: 5, name: 'vs2', attr: 'address offsets'}, {bits: 1, name: 'vm'}, {bits: 2, name: 'mop'}, {bits: 1, name: 'mew'}, diff --git a/src/images/wavedrom/vtype-format.adoc b/src/images/wavedrom/vtype-format.edn index 9e6ab34..9e6ab34 100644 --- a/src/images/wavedrom/vtype-format.adoc +++ b/src/images/wavedrom/vtype-format.edn diff --git a/src/images/wavedrom/wfi.adoc b/src/images/wavedrom/wfi.adoc deleted file mode 100644 index 4447b9f..0000000 --- a/src/images/wavedrom/wfi.adoc +++ /dev/null @@ -1,13 +0,0 @@ -// - -[wavedrom, ,svg] - -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8, attr: ['7','SYSTEM'],}, - {bits: 5, name: 'rd', type: 2, attr: ['5','0'],}, - {bits: 3, name: 'funct3', type: 8, attr: ['3','PRIV'],}, - {bits: 5, name: 'rs1', type: 4, attr: ['5','0'],}, - {bits: 12, name: 'funct12', type: 8, attr: ['12','WFI',]}, -], config: {bits: 32}} -....
\ No newline at end of file diff --git a/src/images/wavedrom/wfi.edn b/src/images/wavedrom/wfi.edn new file mode 100644 index 0000000..870e2a1 --- /dev/null +++ b/src/images/wavedrom/wfi.edn @@ -0,0 +1,13 @@ +// + +[wavedrom, ,svg] + +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7','SYSTEM'],}, + {bits: 5, name: 'rd', attr: ['5','0'],}, + {bits: 3, name: 'funct3', attr: ['3','PRIV'],}, + {bits: 5, name: 'rs1', attr: ['5','0'],}, + {bits: 12, name: 'funct12', attr: ['12','WFI',]}, +], config: {bits: 32}} +....
\ No newline at end of file diff --git a/src/images/wavedrom/zifencei-fetch.adoc b/src/images/wavedrom/zifencei-fetch.adoc deleted file mode 100644 index 42e0d6f..0000000 --- a/src/images/wavedrom/zifencei-fetch.adoc +++ /dev/null @@ -1,12 +0,0 @@ -//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0 - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: 'MISC-MEM', type: 8}, - {bits: 5, name: 'rd', attr: 0}, - {bits: 3, name: 'funct3', attr: 'FENCE.I', type: 8}, - {bits: 5, name: 'rs1', attr: 0}, - {bits: 12, name: 'func12', attr: 0}, -]} -.... diff --git a/src/images/wavedrom/zifencei-ff.adoc b/src/images/wavedrom/zifencei-ff.adoc deleted file mode 100644 index 5ccfae0..0000000 --- a/src/images/wavedrom/zifencei-ff.adoc +++ /dev/null @@ -1,12 +0,0 @@ -//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0 - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM'], type: 8}, - {bits: 5, name: 'rd', attr: ['5', '0'], type: 2}, - {bits: 3, name: 'funct3', attr: ['3', 'FENCE.I'], type: 8}, - {bits: 5, name: 'rs1', attr: ['5', '0'], type: 4}, - {bits: 12, name: 'funct12', attr: ['12', '0'], type: 8}, -]} -.... diff --git a/src/images/wavedrom/zifencei-ff.edn b/src/images/wavedrom/zifencei-ff.edn new file mode 100644 index 0000000..24cf87b --- /dev/null +++ b/src/images/wavedrom/zifencei-ff.edn @@ -0,0 +1,12 @@ +//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0 + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM']}, + {bits: 5, name: 'rd', attr: ['5', '0']}, + {bits: 3, name: 'funct3', attr: ['3', 'FENCE.I']}, + {bits: 5, name: 'rs1', attr: ['5', '0']}, + {bits: 12, name: 'funct12', attr: ['12', '0']}, +]} +.... diff --git a/src/images/wavedrom/zihintpause-hint.adoc b/src/images/wavedrom/zihintpause-hint.edn index 4c4a2ed..34c73a7 100644 --- a/src/images/wavedrom/zihintpause-hint.adoc +++ b/src/images/wavedrom/zihintpause-hint.edn @@ -3,9 +3,9 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode', attr: 'MISC-MEM', type: 8}, + {bits: 7, name: 'opcode', attr: 'MISC-MEM'}, {bits: 5, name: 'rd', attr: 0}, - {bits: 3, name: 'funct3', attr: 'PAUSE', type: 8}, + {bits: 3, name: 'funct3', attr: 'PAUSE'}, {bits: 5, name: 'rs1', attr: 0}, {bits: 1, name: 'SW', attr: 0}, {bits: 1, name: 'SR', attr: 0}, |