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| author | elisa <elisa@riscv.org> | 2021-10-19 11:04:33 -0700 |
|---|---|---|
| committer | elisa <elisa@riscv.org> | 2021-10-19 11:04:33 -0700 |
| commit | e57f365c83f562272f3d21777358d6c42d7a9d27 (patch) | |
| tree | fbab64c439b4d42f0297369872713bc6b82b98b6 /src | |
| parent | fd4275ffd26ce0bd301e2e72869cf7f03dde6981 (diff) | |
| download | riscv-isa-manual-e57f365c83f562272f3d21777358d6c42d7a9d27.zip riscv-isa-manual-e57f365c83f562272f3d21777358d6c42d7a9d27.tar.gz riscv-isa-manual-e57f365c83f562272f3d21777358d6c42d7a9d27.tar.bz2 | |
table fixes
Diffstat (limited to 'src')
| -rw-r--r-- | src/c-st-ext.adoc | 25 | ||||
| -rw-r--r-- | src/riscv-isa-unpr-conv-review.pdf | bin | 5778616 -> 5783481 bytes |
2 files changed, 12 insertions, 13 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index d059f2f..decaaff 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -38,8 +38,7 @@ instructions allows significantly greater code density. ==== The compressed instruction encodings are mostly common across RV32C, -RV64C, and RV128C, but as shown in -Table <<rvcopcodemap>>, a few opcodes are used for +RV64C, and RV128C, but as shown in <<rvcopcodemap>>, a few opcodes are used for different purposes depending on base ISA. For example, the wider address-space RV64C and RV128C variants require additional opcodes to compress loads and stores of 64-bit integer values, while RV32C uses the @@ -173,10 +172,10 @@ performance impact as doubling the instruction cache size. === Compressed Instruction Formats (((compressed, formats))) -Table <<rvcopcodemap>> shows the nine compressed instruction +<<rvcopcodemap>> shows the nine compressed instruction formats. CR, CI, and CSS can use any of the 32 RVI registers, but CIW, CL, CS, CA, and CB are limited to just 8 of them. -Table <<registers>> lists these popular registers, which +<<registers>> lists these popular registers, which correspond to registers _x8_ to _x15_. Note that there is a separate version of load and store instructions that use the stack pointer as the base address register, since saving to and restoring from the stack are @@ -234,10 +233,10 @@ image::image_placeholder.png[] [[rvc-form]] .Compressed 16-bit RVC instruction formats. -[%header,cols="^,^,<,<,<,<,<,"] +[%header,cols="^,^,^,^,^,^,^,"] |=== -|Format |Meaning 2+|15 14 13 12 |11 10 9 8 7 2+|6 5 4 3 2 | 1 0 +|Format |Meaning 2+^|15 14 13 12 ^|11 10 9 8 7 2+^|6 5 4 3 2 ^| 1 0 |CR |Register 2+|funct4| rd/rs1 2+|rs2 | op @@ -259,9 +258,7 @@ image::image_placeholder.png[] |=== [registers] -.Registers specified by the three-bit _rs1 l'_, -_rs2 l'_, and _rd l'_ fields of the CIW, CL, -CS, CA, and CB formats. +.Registers specified by the three-bit _rs1 l'_, _rs2 l'_, and _rd l'_ fields of the CIW, CL, CS, CA, and CB formats. [%header,cols="20%,10%,10%,10%,10%,10%,10%,10%,10%"] |=== |RVC Register Number |000 |001 |010 |011 |100 |101 |110 |111 @@ -921,6 +918,7 @@ no standard HINTs will ever be defined in this subspace. [cols="<,<,>,<",options="header",] |=== |Instruction |Constraints |Code Points |Purpose + |C.NOP |_nzimm_≠0 |63 .6+^.>s|_Reserved for future standard use_ |C.ADDI | _rd_≠_x0_, _nzimm_=0 |31 @@ -959,7 +957,7 @@ microarchitectural hints <<rvc-hints>>. [[rvcopcodemap]] .RVC opcode map instructions. -[cols=">,^,^,^,^,^,^,^,^,^,<"] +[cols="20%,6%,8%,6%,6%,6%,6%,6%,6%,5%] |=== |inst[15:13] .2+^.>s|000 .2+^.>s|001 .2+^.>s|010 .2+^.>s|011 .2+^.>s|100 .2+^.>s|101 .2+^.>s|110 .2+^.>s|111 .2+^.>s| |inst[1:0] @@ -980,7 +978,7 @@ microarchitectural hints <<rvc-hints>>. [%header,format+DSV,separator=!,cols="10%,12%,12%,12%,6%,5%,41%"] !=== -!15 14 13 3+! 12 11 10 9 8 7 6 5 !4 3 2 ! 1 0 ! +^!15 14 13 3+^! 12 11 10 9 8 7 6 5 ^!4 3 2 ^! 1 0 ! !000 3+!0 ! 0 !00 !_Illegal instruction_ @@ -1015,7 +1013,7 @@ microarchitectural hints <<rvc-hints>>. [%header,format+DSV,separator=!,cols="2,3,2,2,2,2,2,6"] !=== -! 15 14 13 ! 12 2+! 11 10 9 8 7 2+! 6 5 4 3 2 ! 1 0 ! +^! 15 14 13 ^! 12 2+^! 11 10 9 8 7 2+^! 6 5 4 3 2 ^! 1 0 ! !000 !nzimm[5] 2+!0 2+!nzimm[4:0] !01 !C.NOP _(HINT,nzimm ≠0)_ @@ -1069,7 +1067,7 @@ microarchitectural hints <<rvc-hints>>. .Instruction listing for RVC, Quadrant 2 [%header,format+DSV,separator=!,cols="10%,14%,14%,16%,5%,41%"] !=== -!15 14 13 !12 !11 10 9 8 7! 6 5 4 3 2 !1 0 ! +^!15 14 13 ^!12 ^!11 10 9 8 7 ^! 6 5 4 3 2 ^!1 0 ! !000! nzuimm[5]! rs1/rd̸=0 ! nzuimm[4:0] ! 10 ! C.SLLI _(HINT, rd=0; RV32 Custom, nzuimm[5]=1)_ @@ -1102,6 +1100,7 @@ microarchitectural hints <<rvc-hints>>. !110 2+! uimm[5:2|7:6]! rs2 ! 10! C.SWSP !111 2+! uimm[5:2|7:6]! rs2 ! 10 !C.FSWSP _(RV32)_ + !111 2+! uimm[5:3|8:6]! rs2 ! 10 !C.SDSP _(RV64/128)_ !=== diff --git a/src/riscv-isa-unpr-conv-review.pdf b/src/riscv-isa-unpr-conv-review.pdf Binary files differindex 61abdf5..e4a310e 100644 --- a/src/riscv-isa-unpr-conv-review.pdf +++ b/src/riscv-isa-unpr-conv-review.pdf |