Clarify that timer/cofi interrupts may arrive delayed in xip

4 files changed, 12 insertions, 7 deletions

diff --git a/src/machine.adoc b/src/machine.adoc
index cd2159b..c03fe83 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -2383,8 +2383,9 @@ Simple fixed-frequency systems can use a single clock for both cycle
 counting and wall-clock time.
 ====
 
-Writes to `mtime` and `mtimecmp` are guaranteed to be reflected in MTIP
-eventually, but not necessarily immediately.
+If the result of the comparison between `mtime` and `mtimecmp` changes, it is
+guaranteed to be reflected in MTIP eventually, but not necessarily
+immediately.
 
 [NOTE]
 ====
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc
index 55d9db6..4fffdcb 100644
--- a/src/priv-preface.adoc
+++ b/src/priv-preface.adoc
@@ -112,6 +112,8 @@ be set to a nonzero value but sometimes not.
 * Clarified exception behavior of unimplemented or inaccessible CSRs.
 * Clarified that Svpbmt allows implementations to override additional PMAs.
 * Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.
+* Clarified that timer and count-overflow interrupts' arrival in
+  interrupt-pending registers is not immediate.
 
 [.big]*_Preface to Version 20211203_*
 
diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc
index c1207e5..84f1a09 100644
--- a/src/sscofpmf.adoc
+++ b/src/sscofpmf.adoc
@@ -78,7 +78,9 @@ interrupt-pending and interrupt-enable bits for this interrupt.
 ('LCOFI' represents 'Local Count Overflow Interrupt'.)
 
 Generation of a count-overflow-interrupt request by an `hpmcounter` sets the
-associated OF bit and sets the LCOFIP bit in the `mip`/`sip` registers.
+associated OF bit.
+When an OF bit is set, it eventually, but not necessarily immediately, sets
+the LCOFIP bit in the `mip`/`sip` registers.
 The LCOFIP bit is cleared by software before servicing the count overflow
 interrupt resulting from one or more count overflows.
 The `mideleg` register controls the delegation of this interrupt to S-mode
diff --git a/src/sstc.adoc b/src/sstc.adoc
index 399d556..49be41a 100644
--- a/src/sstc.adoc
+++ b/src/sstc.adoc
@@ -41,8 +41,8 @@ Supervisor Trap Setup block of CSRs).
 A supervisor timer interrupt becomes pending, as reflected in the STIP bit in
 the `mip` and `sip` registers whenever `time` contains a value greater than or
 equal to `stimecmp`, treating the values as unsigned integers.
-Writes to `stimecmp` are guaranteed to be reflected in STIP eventually, but
-not necessarily immediately.
+If the result of this comparison changes, it is guaranteed to be reflected in
+STIP eventually, but not necessarily immediately.
 The interrupt remains posted until `stimecmp` becomes greater than `time`,
 typically as a result of writing `stimecmp`.
 The interrupt will be taken based on the standard interrupt enable and
@@ -128,8 +128,8 @@ A virtual supervisor timer interrupt becomes pending, as reflected in the
 VSTIP bit in the `hip` register, whenever (`time` + `htimedelta`), truncated
 to 64 bits, contains a value greater than or equal to `vstimecmp`, treating
 the values as unsigned integers.
-Writes to `vstimecmp` and `htimedelta` are guaranteed to be reflected in VSTIP
-eventually, but not necessarily immediately.
+If the result of this comparison changes, it is guaranteed to be reflected in
+VSTIP eventually, but not necessarily immediately.
 The interrupt remains posted until `vstimecmp` becomes greater than (`time`
 + `htimedelta`), typically as a result of writing `vstimecmp`.
 The interrupt will be taken based on the standard interrupt enable and