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| author | Andrew Waterman <andrew@sifive.com> | 2019-01-22 13:34:40 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-01-22 13:35:03 -0800 |
| commit | c18f59082c072279dc6e24f9f43100a81f5a9340 (patch) | |
| tree | 1c6801bc45002088a58d41bd3e86705a5aab563e /src | |
| parent | 0bfd3e17b34dcc0be8df7d0b7a42a1d4d6a26010 (diff) | |
| download | riscv-isa-manual-c18f59082c072279dc6e24f9f43100a81f5a9340.zip riscv-isa-manual-c18f59082c072279dc6e24f9f43100a81f5a9340.tar.gz riscv-isa-manual-c18f59082c072279dc6e24f9f43100a81f5a9340.tar.bz2 | |
Nest mstatus subsections
h/t Dan Hopper
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 10 | ||||
| -rw-r--r-- | src/riscv-privileged.tex | 3 |
2 files changed, 8 insertions, 5 deletions
diff --git a/src/machine.tex b/src/machine.tex index 41847f5..e4753cc 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -509,7 +509,7 @@ ISAs respectively. \end{figure*} -\subsection{Privilege and Global Interrupt-Enable Stack in {\tt mstatus} register} +\subsubsection{Privilege and Global Interrupt-Enable Stack in {\tt mstatus} register} \label{privstack} Global interrupt-enable bits, MIE, SIE, and UIE, are provided for each @@ -592,7 +592,7 @@ supported in systems running Unix-like operating systems to support user-level trap handling. \end{commentary} -\subsection{Base ISA Control in {\tt mstatus} Register} +\subsubsection{Base ISA Control in {\tt mstatus} Register} \label{xlen-control} For RV64 systems, the SXL and UXL fields are \warl\ fields @@ -635,7 +635,7 @@ If MXLEN is changed from 32 to a wider width, each of {\tt mstatus} fields SXL a UXL, if not hardwired to a forced value, gets the value corresponding to the widest supported width not wider than the new MXLEN. -\subsection{Memory Privilege in {\tt mstatus} Register} +\subsubsection{Memory Privilege in {\tt mstatus} Register} The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads and stores execute in all privilege modes. When MPRV=0, loads and stores @@ -677,7 +677,7 @@ Note that, while SUM is ordinarily ignored when not executing in S-mode, it {\em is} in effect when MPRV=1 and MPP=S. SUM is hardwired to 0 if S-mode is not supported. -\subsection{Virtualization Support in {\tt mstatus} Register} +\subsubsection{Virtualization Support in {\tt mstatus} Register} \label{virt-control} The TVM (Trap Virtual Memory) bit supports intercepting @@ -730,7 +730,7 @@ Trapping SRET is necessary to emulate the hypervisor extension (see Chapter~\ref{hypervisor}) on implementations that do not provide it. \end{commentary} -\subsection{Extension Context Status in {\tt mstatus} Register} +\subsubsection{Extension Context Status in {\tt mstatus} Register} Supporting substantial extensions is one of the primary goals of RISC-V, and hence we define a standard interface to allow unchanged diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex index 4b2bba3..cd5d878 100644 --- a/src/riscv-privileged.tex +++ b/src/riscv-privileged.tex @@ -9,6 +9,9 @@ \newcommand{\privrev}{\mbox{20190125-Public-Review-{\em draft}}} \newcommand{\privmonthyear}{\mbox{January 2019}} +\setcounter{secnumdepth}{3} +\setcounter{tocdepth}{3} + \begin{document} \title{\vspace{-0.7in}\Large {\bf The RISC-V Instruction Set Manual} \\ |