State that mtime -> time has propagation delay (#1514)riscv-isa-release-bc6a9b7-2024-07-23riscv-isa-release-b001864-2024-07-23riscv-isa-release-05175a7-2024-07-23

1 files changed, 8 insertions, 2 deletions

diff --git a/src/machine.adoc b/src/machine.adoc
index a81f7bb..24a0a75 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -1575,9 +1575,9 @@ counters, the counters can be directly exposed to lower privilege modes.
 The `cycle`, `instret`, and `hpmcountern` CSRs are read-only shadows of
 `mcycle`, `minstret`, and `mhpmcounter n`, respectively. The `time` CSR
 is a read-only shadow of the memory-mapped `mtime` register.
-Analogously, on RV32I the `cycleh`, `instreth` and `hpmcounternh` CSRs
+Analogously, when XLEN=32, the `cycleh`, `instreth` and `hpmcounternh` CSRs
 are read-only shadows of `mcycleh`, `minstreth` and `mhpmcounternh`,
-respectively. On RV32I the `timeh` CSR is a read-only shadow of the
+respectively. When XLEN=32, the `timeh` CSR is a read-only shadow of the
 upper 32 bits of the memory-mapped `mtime` register, while `time`
 shadows only the lower 32 bits of `mtime`.
 
@@ -2336,6 +2336,12 @@ For RV64, naturally aligned 64-bit memory accesses to the `mtime` and
 ....
 
 
+The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.
+When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the
+memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of
+`mtime`.
+When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh`
+eventually, but not necessarily immediately.
 
 
 === Machine-Mode Privileged Instructions