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author | Andrew Waterman <andrew@sifive.com> | 2019-11-06 00:35:13 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-11-06 00:35:13 -0800 |
commit | a7cf36df81cf938919eede162c7ff0fc88b28e91 (patch) | |
tree | 9eb2b70cadefe3856ff59126bf3841f3b3fc7aa8 /src | |
parent | 47745d937e4ad9dbf02571fd083a716f528ca5df (diff) | |
download | riscv-isa-manual-a7cf36df81cf938919eede162c7ff0fc88b28e91.zip riscv-isa-manual-a7cf36df81cf938919eede162c7ff0fc88b28e91.tar.gz riscv-isa-manual-a7cf36df81cf938919eede162c7ff0fc88b28e91.tar.bz2 |
Convert samepage-commentary blocks to commentary blocks
Diffstat (limited to 'src')
-rw-r--r-- | src/d.tex | 4 | ||||
-rw-r--r-- | src/intro.tex | 4 | ||||
-rw-r--r-- | src/machine.tex | 4 | ||||
-rw-r--r-- | src/preamble.tex | 4 | ||||
-rw-r--r-- | src/supervisor.tex | 4 |
5 files changed, 8 insertions, 12 deletions
@@ -33,7 +33,7 @@ Valid NaN-boxed $n$-bit values therefore appear as negative quiet NaNs register must write all 1s to the uppermost FLEN$-n$ bits to yield a legal NaN-boxed value. -\begin{samepage-commentary} +\begin{commentary} Software might not know the current type of data stored in a floating-point register but has to be able to save and restore the register values, hence the result of using wider operations to @@ -41,7 +41,7 @@ transfer narrower values has to be defined. A common case is for callee-saved registers, but a standard convention is also desirable for features including varargs, user-level threading libraries, virtual machine migration, and debugging. -\end{samepage-commentary} +\end{commentary} Floating-point $n$-bit transfer operations move external values held in IEEE standard formats into and out of the {\tt f} registers, and diff --git a/src/intro.tex b/src/intro.tex index 36d429a..17be148 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -546,7 +546,7 @@ Byte Address: & \multicolumn{1}{r}{base+4} & \multicolumn{1}{r}{base+2} & \multi \label{instlengthcode} \end{figure} -\begin{samepage-commentary} +\begin{commentary} Given the code size and energy savings of a compressed format, we wanted to build in support for a compressed format to the ISA encoding scheme rather than adding this as an afterthought, but to allow @@ -574,7 +574,7 @@ spaces into the 32-bit fixed-width format, while preserving support for standard $\geq$32-bit instruction-set extensions. Further, if the implementation also does not need instructions $>$32-bits in length, it can recover a further four major opcodes for non-conforming extensions. -\end{samepage-commentary} +\end{commentary} Encodings with bits [15:0] all zeros are defined as illegal instructions. These instructions are considered to be of minimal diff --git a/src/machine.tex b/src/machine.tex index d66657e..bfdf8c6 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1784,7 +1784,7 @@ mcycleh}, {\tt minstreth}, and {\tt mhpmcounter{\em n}h} CSRs return bits %On RV128 systems, the 64-bit values in {\tt mcycle}, {\tt minstret}, and %{\tt mhpmcounter{\em n}} are sign-extended to 128-bits when read. -%\begin{samepage-commentary} +%\begin{commentary} %On RV128 systems, both signed and unsigned 64-bit values are held in a %canonical form with bit 63 repeated in all higher bit positions. The %counters are 64-bit values even in RV128, and so the counter CSR reads @@ -1793,7 +1793,7 @@ mcycleh}, {\tt minstreth}, and {\tt mhpmcounter{\em n}h} CSRs return bits %to experience wraparound (e.g., $2^{63}$ instructions executed) %and thereby avoid having to actually implement the sign-extension %circuitry. -%\end{samepage-commentary} +%\end{commentary} \subsection{Counter-Enable Registers ({\tt [m|s]counteren})} \label{sec:mcounteren} diff --git a/src/preamble.tex b/src/preamble.tex index 1948407..89cbd2d 100644 --- a/src/preamble.tex +++ b/src/preamble.tex @@ -77,10 +77,6 @@ } {\endlist} -\newenvironment{samepage-commentary} -{\begin{samepage} \begin{commentary}} -{\end{commentary} \end{samepage}} - %\newenvironment{discussion} %{ \vspace{-1.5mm} % \list{}{ diff --git a/src/supervisor.tex b/src/supervisor.tex index e2c8781..677498b 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -838,13 +838,13 @@ values Bare, Sv39, and Sv48.} \label{rv64satp} \end{figure} -\begin{samepage-commentary} +\begin{commentary} We store the ASID and the page table base address in the same CSR to allow the pair to be changed atomically on a context switch. Swapping them non-atomically could pollute the old virtual address space with new translations, or vice-versa. This approach also slightly reduces the cost of a context switch. -\end{samepage-commentary} +\end{commentary} Table~\ref{tab:satp-mode} shows the encodings of the MODE field for RV32 and RV64. When MODE=Bare, supervisor virtual addresses are equal to |