diff options
| author | elisa <elisa@riscv.org> | 2021-09-21 12:28:28 -0700 |
|---|---|---|
| committer | elisa <elisa@riscv.org> | 2021-09-21 12:28:28 -0700 |
| commit | a34a120882d7b6857e97e4c886daa947980c285d (patch) | |
| tree | 158ce1e156fed6370b46c391cebbb48721403992 /src | |
| parent | 5ff58943dbb2961e37fb0123883bcaeb7337d4ca (diff) | |
| download | riscv-isa-manual-a34a120882d7b6857e97e4c886daa947980c285d.zip riscv-isa-manual-a34a120882d7b6857e97e4c886daa947980c285d.tar.gz riscv-isa-manual-a34a120882d7b6857e97e4c886daa947980c285d.tar.bz2 | |
adding some diagram files, adding changes, updating review pdf
Diffstat (limited to 'src')
40 files changed, 739 insertions, 9285 deletions
diff --git a/src/d-st-ext.adoc b/src/d-st-ext.adoc index b2ea945..1b8768d 100644 --- a/src/d-st-ext.adoc +++ b/src/d-st-ext.adoc @@ -5,7 +5,7 @@ instruction-set extension, which is named `D` and adds double-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard. The D extension depends on the base single-precision instruction subset F. -((double-precision floaing point)) +((double-precision, floating point)) === D Register State @@ -14,9 +14,12 @@ The D extension widens the 32 floating-point registers, `f0`–` f31`, to now hold either 32-bit or 64-bit floating-point values as described below in <<nanboxing>>. +[NOTE] +==== FLEN can be 32, 64, or 128 depending on which of the F, D, and Q extensions are supported. There can be up to four different floating-point precisions supported, including H, F, D, and Q. +==== (((floating-point, supported precisions))) [[nanboxing]] @@ -34,7 +37,8 @@ the uppermost FLENlatexmath:[$-n$] bits to yield a legal NaN-boxed value. (((floating-point, requirements))) - +[NOTE] +==== Software might not know the current type of data stored in a floating-point register but has to be able to save and restore the register values, hence the result of using wider operations to transfer @@ -42,6 +46,7 @@ narrower values has to be defined. A common case is for callee-saved registers, but a standard convention is also desirable for features including varargs, user-level threading libraries, virtual machine migration, and debugging. +==== Floating-point latexmath:[$n$]-bit transfer operations move external values held in IEEE standard formats into and out of the `f` registers, @@ -62,6 +67,8 @@ so, the latexmath:[$n$] least-significant bits of the input are used as the input value, otherwise the input value is treated as an latexmath:[$n$]-bit canonical NaN. +[TIP] +==== Earlier versions of this document did not define the behavior of feeding the results of narrower or wider operands into an operation, except to require that wider saves and restores would preserve the value of a @@ -90,6 +97,7 @@ to handle shifting of input subnormal values for wide operands in any case, and extracting the NaN-boxed value is a similar process to normalization except for skipping over leading-1 bits instead of skipping over leading-0 bits, allowing the datapath muxing to be shared. +==== [[fld_fsd]] === Double-Precision Load and Store Instructions @@ -98,21 +106,15 @@ The FLD instruction loads a double-precision floating-point value from memory into floating-point register _rd_. FSD stores a double-precision value from the floating-point registers to memory. +[NOTE] +==== The double-precision value may be a NaN-boxed single-precision value. +==== -[[fprs-d]] - -M@R@F@R@O + -& & & & + -& & & & + -& 5 & 3 & 5 & 7 + -offset[11:0] & base & D & dest & LOAD-FP + - -O@R@R@F@R@O + -& & & & & + -& & & & & + -& 5 & 5 & 3 & 5 & 7 + -offset[11:5] & src & base & D & offset[4:0] & STORE-FP + +include::images/wavedrom/double-ls.adoc[] +[[double-ls]] +.Double-precision load and store +image::image_placeholder.png[] FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLENlatexmath:[$\geq$]64. @@ -126,20 +128,10 @@ The double-precision floating-point computational instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands and produce double-precision results. -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FADD/FSUB & D & src2 & src1 & RM & dest & OP-FP + -FMUL/FDIV & D & src2 & src1 & RM & dest & OP-FP + -FMIN-MAX & D & src2 & src1 & MIN/MAX & dest & OP-FP + -FSQRT & D & 0 & src & RM & dest & OP-FP + - -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -src3 & D & src2 & src1 & RM & dest & F[N]MADD/F[N]MSUB + +include::images/wavedrom/double-fl-compute.adoc[] +[[fl-compute]] +.Double-precision float computational +image::image_placeholder.png[] === Double-Precision Floating-Point Conversion and Move Instructions @@ -160,12 +152,10 @@ All floating-point to integer and integer to floating-point conversion instructions round according to the _rm_ field. Note FCVT.D.W[U] always produces an exact result and is unaffected by rounding mode. -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FCVT._int_.D & D & W[U]/L[U] & src & RM & dest & OP-FP + -FCVT.D._int_ & D & W[U]/L[U] & src & RM & dest & OP-FP + +include::images/wavedrom/double-fl-convert-mv.adoc[] +[[fl-convert-mv]] +.Double-precision float convert and move +image::image_placeholder.png[] The double-precision to single-precision and single-precision to double-precision conversion instructions, FCVT.S.D and FCVT.D.S, are @@ -175,22 +165,19 @@ datatype of the source, and the _fmt_ field encodes the datatype of the destination. FCVT.S.D rounds according to the RM field; FCVT.D.S will never round. -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FCVT.S.D & S & D & src & RM & dest & OP-FP + -FCVT.D.S & D & S & src & RM & dest & OP-FP + +include::images/wavedrom/fcvt-sd-ds.adoc[] +[[fcvt-sd-ds]] +.Double-precision FCVT.S.D and FCVT.D.S +image::image_placeholder.png[] Floating-point to floating-point sign-injection instructions, FSGNJ.D, FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision sign-injection instruction. +//FSGNJ.D, FSGNJN.D, and FSGNJX.D -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FSGNJ & D & src2 & src1 & J[N]/JX & dest & OP-FP + +include::images/wavedrom/fsjgnjnx-d.adoc[] +.Double-precision sign-injection +image::image_placeholder.png[] For XLENlatexmath:[$\geq$]64 only, instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.D moves @@ -203,13 +190,13 @@ register _rd_. FMV.X.D and FMV.D.X do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FMV.X.D & D & 0 & src & 000 & dest & OP-FP + -FMV.D.X & D & 0 & src & 000 & dest & OP-FP + +include::images/wavedrom/d-xwwx.adoc[] +[[fmvxddx]] +.Double-precision float move to _rd_ +image::image_placeholder.png[] +[TIP] +==== Early versions of the RISC-V ISA had additional instructions to allow RV32 systems to transfer between the upper and lower portions of a 64-bit floating-point register and an integer register. However, these @@ -229,6 +216,7 @@ stores, the marginal hardware cost of moving from a 32-bit to a 64-bit integer datapath is low, and a software ABI supporting 32-bit wide address-space and pointers can be used to avoid growth of static data and dynamic memory traffic. +==== === Double-Precision Floating-Point Compare Instructions @@ -236,11 +224,10 @@ The double-precision floating-point compare instructions are defined analogously to their single-precision counterparts, but operate on double-precision operands. -S@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FCMP & D & src2 & src1 & EQ/LT/LE & dest & OP-FP + +include::images/wavedrom/double-fl-compare.adoc[] +[[fl-compare]] +.Double-precision float compare +image::image_placeholder.png[] === Double-Precision Floating-Point Classify Instruction @@ -248,8 +235,9 @@ The double-precision floating-point classify instruction, FCLASS.D, is defined analogously to its single-precision counterpart, but operates on double-precision operands. -S@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FCLASS & D & 0 & src & 001 & dest & OP-FP + +include::images/wavedrom/double-fl-class.adoc[] +[[fl-class]] +.Double-precision float classify +image::image_placeholder.png[] + + diff --git a/src/graphviz/litmus_addrpo.dot b/src/graphviz/litmus_addrpo.dot deleted file mode 100644 index d61fd5e..0000000 --- a/src/graphviz/litmus_addrpo.dot +++ /dev/null @@ -1,30 +0,0 @@ -digraph G { - -splines=spline; -pad="0.000000"; - - -/* the unlocked events */ -eiid0 [label="a: Ry=1", shape="none", fontsize=8, pos="1.000000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid1 [label="c: Wx=t", shape="none", fontsize=8, pos="1.000000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid2 [label="d: Rx=t", shape="none", fontsize=8, pos="2.500000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid3 [label="e: Rt=$v$", shape="none", fontsize=8, pos="2.500000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid4 [label="f: Wy=1", shape="none", fontsize=8, pos="2.500000,0.000000!", fixedsize="false", height="0.111111", width="0.555556"]; - -/* the intra_causality_data edges */ - - -/* the intra_causality_control edges */ - -/* the poi edges */ -/* the rfmap edges */ - - -/* The viewed-before edges */ -eiid0 -> eiid1 [label=<<font color="darkgreen">fence</font><font color="indigo">ppo</font>>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid1 -> eiid2 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid2 -> eiid3 [label=<<font color="indigo">addr</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid2 -> eiid4 [label=<<font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid3 -> eiid4 [label=<<font color="black">po</font>>, color="black", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid4 -> eiid0 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -} diff --git a/src/graphviz/litmus_datacoirfi.dot b/src/graphviz/litmus_datacoirfi.dot deleted file mode 100644 index df8ea72..0000000 --- a/src/graphviz/litmus_datacoirfi.dot +++ /dev/null @@ -1,33 +0,0 @@ -digraph G { - -splines=spline; -pad="0.000000"; - - -/* the unlocked events */ -eiid0 [label="a: Wx=1", shape="none", fontsize=8, pos="1.000000,2.250000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid1 [label="c: Wy=1", shape="none", fontsize=8, pos="1.000000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid2 [label="d: Ry=1", shape="none", fontsize=8, pos="2.500000,3.093750!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid3 [label="e: Wz=1", shape="none", fontsize=8, pos="2.500000,2.531250!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid4 [label="f: Wz=1", shape="none", fontsize=8, pos="2.500000,1.968750!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid5 [label="g: Rz=1", shape="none", fontsize=8, pos="2.500000,1.406250!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid6 [label="h: Rx=0", shape="none", fontsize=8, pos="2.500000,0.843750!", fixedsize="false", height="0.111111", width="0.555556"]; - -/* the intra_causality_data edges */ - - -/* the intra_causality_control edges */ - -/* the poi edges */ -/* the rfmap edges */ - - -/* The viewed-before edges */ -eiid0 -> eiid1 [label=<<font color="darkgreen">fence</font><font color="indigo">ppo</font>>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid1 -> eiid2 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid2 -> eiid3 [label=<<font color="indigo">data</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid3 -> eiid4 [label=<<font color="blue">co</font><font color="indigo">ppo</font>>, color="bluf:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid4 -> eiid5 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid5 -> eiid6 [label=<<font color="indigo">addr</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid6 -> eiid0 [label=<<font color="#ffa040">fr</font>>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -} diff --git a/src/graphviz/litmus_datarfi.dot b/src/graphviz/litmus_datarfi.dot deleted file mode 100644 index 88106e3..0000000 --- a/src/graphviz/litmus_datarfi.dot +++ /dev/null @@ -1,32 +0,0 @@ -digraph G { - -splines=spline; -pad="0.000000"; - - -/* the unlocked events */ -eiid0 [label="a: Wx=1", shape="none", fontsize=8, pos="1.000000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid1 [label="c: Wy=1", shape="none", fontsize=8, pos="1.000000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid2 [label="d: Ry=1", shape="none", fontsize=8, pos="2.500000,2.250000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid3 [label="e: Wz=1", shape="none", fontsize=8, pos="2.500000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid4 [label="f: Rz=1", shape="none", fontsize=8, pos="2.500000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid5 [label="g: Rx=0", shape="none", fontsize=8, pos="2.500000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; - -/* the intra_causality_data edges */ - - -/* the intra_causality_control edges */ - -/* the poi edges */ -/* the rfmap edges */ - - -/* The viewed-before edges */ -eiid0 -> eiid1 [label=<<font color="darkgreen">fence</font><font color="indigo">ppo</font>>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid1 -> eiid2 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid2 -> eiid3 [label=<<font color="indigo">data</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid2 -> eiid4 [label=<<font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid3 -> eiid4 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid4 -> eiid5 [label=<<font color="indigo">addr</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid5 -> eiid0 [label=<<font color="#ffa040">fr</font>>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -} diff --git a/src/graphviz/litmus_lb_lrsc.dot b/src/graphviz/litmus_lb_lrsc.dot deleted file mode 100644 index 0a6c4ca..0000000 --- a/src/graphviz/litmus_lb_lrsc.dot +++ /dev/null @@ -1,32 +0,0 @@ -digraph G { - -splines=spline; -pad="0.000000"; - - -/* the unlocked events */ -eiid0 [label="a: Rx=0", shape="none", fontsize=8, pos="1.000000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid1 [label="b: Rz*=0", shape="none", fontsize=8, pos="1.000000,1.125000!", fixedsize="false", height="0.111111", width="0.666667"]; -eiid2 [label="c: Wz*=0", shape="none", fontsize=8, pos="1.000000,0.562500!", fixedsize="false", height="0.111111", width="0.666667"]; -eiid3 [label="d: Wy=0", shape="none", fontsize=8, pos="1.000000,0.000000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid4 [label="e: Ry=0", shape="none", fontsize=8, pos="2.500000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid5 [label="f: Wx=0", shape="none", fontsize=8, pos="2.500000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; - -/* the intra_causality_data edges */ - - -/* the intra_causality_control edges */ - -/* the poi edges */ -/* the rfmap edges */ - - -/* The viewed-before edges */ -eiid0 -> eiid1 [label=<<font color="black">po</font>>, color="black", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid0 -> eiid2 [label=<<font color="indigo">data</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid1 -> eiid2 [label=<<font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid2 -> eiid3 [label=<<font color="indigo">data</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid3 -> eiid4 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid4 -> eiid5 [label=<<font color="indigo">data</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid5 -> eiid0 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -} diff --git a/src/graphviz/litmus_mp_fenceww_fri_rfi_addr.dot b/src/graphviz/litmus_mp_fenceww_fri_rfi_addr.dot deleted file mode 100644 index e56599b..0000000 --- a/src/graphviz/litmus_mp_fenceww_fri_rfi_addr.dot +++ /dev/null @@ -1,32 +0,0 @@ -digraph G { - -splines=spline; -pad="0.000000"; - - -/* the unlocked events */ -eiid0 [label="a: Wx=1", shape="none", fontsize=8, pos="1.000000,1.575000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid1 [label="c: Wy=1", shape="none", fontsize=8, pos="1.000000,1.050000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid2 [label="d: Ry=1", shape="none", fontsize=8, pos="2.500000,1.575000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid3 [label="e: Wy=2", shape="none", fontsize=8, pos="2.500000,1.050000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid4 [label="f: Ry=2", shape="none", fontsize=8, pos="2.500000,0.525000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid5 [label="i: Rx=0", shape="none", fontsize=8, pos="2.500000,0.000000!", fixedsize="false", height="0.111111", width="0.555556"]; - -/* the intra_causality_data edges */ - - -/* the intra_causality_control edges */ - -/* the poi edges */ -/* the rfmap edges */ - - -/* The viewed-before edges */ -eiid0 -> eiid1 [label=<<font color="darkgreen">fence</font><font color="indigo">ppo</font>>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid1 -> eiid2 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid1 -> eiid3 [label=<<font color="blue">co</font>>, color="blue", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid2 -> eiid3 [label=<<font color="#ffa040">fr</font><font color="indigo">ppo</font>>, color="#ffa040:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid3 -> eiid4 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid4 -> eiid5 [label=<<font color="indigo">addr</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid5 -> eiid0 [label=<<font color="#ffa040">fr</font>>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -} diff --git a/src/graphviz/litmus_rsw.dot b/src/graphviz/litmus_rsw.dot deleted file mode 100644 index 9142351..0000000 --- a/src/graphviz/litmus_rsw.dot +++ /dev/null @@ -1,34 +0,0 @@ -digraph G { - -splines=spline; -pad="0.000000"; - - -/* the unlocked events */ -eiid0 [label="a: Wx=1", shape="none", fontsize=8, pos="1.000000,2.025000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid1 [label="c: Wy=1", shape="none", fontsize=8, pos="1.000000,1.575000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid2 [label="d: Ry=1", shape="none", fontsize=8, pos="2.000000,2.025000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid3 [label="g: Rz=$v$", shape="none", fontsize=8, pos="2.000000,1.575000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid4 [label="h: Rz=$v$", shape="none", fontsize=8, pos="2.000000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid5 [label="k: Rx=0", shape="none", fontsize=8, pos="2.000000,0.675000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid6 [label=" Wz=$v$", shape="none", fontsize=8, pos="3.000000,1.350000!", fixedsize="false", height="0.111111", width="0.555556"]; - -/* the intra_causality_data edges */ - - -/* the intra_causality_control edges */ - -/* the poi edges */ -/* the rfmap edges */ - - -/* The viewed-before edges */ -eiid0 -> eiid1 [label=<<font color="darkgreen">fence</font><font color="indigo">ppo</font>>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid1 -> eiid2 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid2 -> eiid3 [label=<<font color="indigo">addr</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid3 -> eiid4 [label=<<font color="black">po</font>>, color="black", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid4 -> eiid5 [label=<<font color="indigo">addr</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid5 -> eiid0 [label=<<font color="#ffa040">fr</font>>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid6 -> eiid3 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid6 -> eiid4 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -} diff --git a/src/graphviz/litmus_subsumption.dot b/src/graphviz/litmus_subsumption.dot deleted file mode 100644 index 75e0a70..0000000 --- a/src/graphviz/litmus_subsumption.dot +++ /dev/null @@ -1,29 +0,0 @@ -digraph G { - -splines=spline; -pad="0.000000"; - - -/* the unlocked events */ -eiid0 [label="a: Wx=3", shape="none", fontsize=8, pos="1.000000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid1 [label="b: Wy=1", shape="none", fontsize=8, pos="1.000000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid2 [label="c: Ry=1", shape="none", fontsize=8, pos="2.500000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid3 [label="d: Wx=1", shape="none", fontsize=8, pos="2.500000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; -eiid4 [label="e: Wx=2", shape="none", fontsize=8, pos="2.500000,0.000000!", fixedsize="false", height="0.111111", width="0.555556"]; - -/* the intra_causality_data edges */ - - -/* the intra_causality_control edges */ - -/* the poi edges */ -/* the rfmap edges */ - - -/* The viewed-before edges */ -eiid0 -> eiid1 [label=<<font color="darkgreen">fence</font><font color="indigo">ppo</font>>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid0 -> eiid3 [label=<<font color="blue">co</font>>, color="blue", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid1 -> eiid2 [label=<<font color="red">rf</font>>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid2 -> eiid3 [label=<<font color="indigo">data</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -eiid3 -> eiid4 [label=<<font color="blue">co</font><font color="indigo">ppo</font>>, color="blue:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; -} diff --git a/src/images/f-standard.png b/src/images/f-standard.png Binary files differnew file mode 100644 index 0000000..9a0a2c1 --- /dev/null +++ b/src/images/f-standard.png diff --git a/src/graphviz/litmus_ppoca.dot b/src/images/graphviz/litmus_ppoca.txt index d512d5f..3ad361c 100644 --- a/src/graphviz/litmus_ppoca.dot +++ b/src/images/graphviz/litmus_ppoca.txt @@ -1,3 +1,5 @@ + +.... digraph G { splines=spline; @@ -31,3 +33,5 @@ eiid3 -> eiid4 [label=<<font color="red">rf</font>>, color="red", fontsize=11, p eiid4 -> eiid5 [label=<<font color="indigo">addr</font><font color="indigo">ppo</font>>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; eiid5 -> eiid0 [label=<<font color="#ffa040">fr</font>>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; } +.... + diff --git a/src/graphviz/litmus_sample.dot b/src/images/graphviz/litmus_sample.txt index 072c8ca..7621050 100644 --- a/src/graphviz/litmus_sample.dot +++ b/src/images/graphviz/litmus_sample.txt @@ -1,3 +1,4 @@ + digraph G { splines=spline; diff --git a/src/graphviz/litmus_sb_fwd.dot b/src/images/graphviz/litmus_sb_fwd.txt index 5434951..dac51f8 100644 --- a/src/graphviz/litmus_sb_fwd.dot +++ b/src/images/graphviz/litmus_sb_fwd.txt @@ -1,3 +1,5 @@ + +.... digraph G { splines=spline; @@ -29,3 +31,5 @@ eiid3 -> eiid4 [label=<<font color="red">rf</font>>, color="red", fontsize=11, p eiid4 -> eiid5 [label=<<font color="darkgreen">fence</font><font color="indigo">ppo</font>>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; eiid5 -> eiid0 [label=<<font color="#ffa040">fr</font>>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; } +... + diff --git a/src/images/wavedrom/d-xwwx.adoc b/src/images/wavedrom/d-xwwx.adoc new file mode 100644 index 0000000..913da9a --- /dev/null +++ b/src/images/wavedrom/d-xwwx.adoc @@ -0,0 +1,19 @@ +//xw-wx + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 0, type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 0, type: 8}, + {bits: 2, name: 'fmt', attr: 'D', type: 8}, + {bits: 5, name: 'funct5', attr: ['FMV.X.W', 'FMV.W.X'], type: 8}, +]} +.... + + + + + diff --git a/src/images/wavedrom/double-fl-class.adoc b/src/images/wavedrom/double-fl-class.adoc new file mode 100644 index 0000000..b57aa8f --- /dev/null +++ b/src/images/wavedrom/double-fl-class.adoc @@ -0,0 +1,15 @@ +//## 13.7 Double-Precision Floating-Point Classify Instruction + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'rm', attr: 1, type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 'rs2', attr: '0', type: 8}, + {bits: 2, name: 'fmt', attr: 'D', type: 8}, + {bits: 5, name: 'funct5', attr: 'FCLASS', type: 8}, +]} +.... + diff --git a/src/images/wavedrom/double-fl-compare.adoc b/src/images/wavedrom/double-fl-compare.adoc new file mode 100644 index 0000000..51f70d9 --- /dev/null +++ b/src/images/wavedrom/double-fl-compare.adoc @@ -0,0 +1,15 @@ +//## 13.6 Double-Precision Floating-Point Compare Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: ['EQ', 'LT', 'LE'], type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'D', type: 8}, + {bits: 5, name: 'funct5', attr: 'FCMP', type: 8}, +]} +.... + diff --git a/src/images/wavedrom/double-fl-compute.adoc b/src/images/wavedrom/double-fl-compute.adoc new file mode 100644 index 0000000..96251e8 --- /dev/null +++ b/src/images/wavedrom/double-fl-compute.adoc @@ -0,0 +1,54 @@ +//## 13.4 Double-Precision Floating-Point Computational Instructions + +[wavedrom, , svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'D', type: 8}, + {bits: 5, name: 'funct5', attr: ['FADD', 'FSUB', 'FMUL', 'FDIV'], type: 8}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 0, type: 8}, + {bits: 2, name: 'fmt', attr: 'D', type: 8}, + {bits: 5, name: 'funct5', attr: 'FSQRT', type: 8}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: ['MIN', 'MAX'], type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'D', type: 8}, + {bits: 5, name: 'funct5', attr: 'FMIN-MAX', type: 8}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'D', type: 8}, + {bits: 5, name: 'rs3', attr: 'src3', type: 4}, +]} +.... + diff --git a/src/images/wavedrom/double-fl-convert-mv.adoc b/src/images/wavedrom/double-fl-convert-mv.adoc new file mode 100644 index 0000000..ac6d7e6 --- /dev/null +++ b/src/images/wavedrom/double-fl-convert-mv.adoc @@ -0,0 +1,16 @@ +//## 13.5 Double-Precision Floating-Point Conversion and Move Instructions + + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 'rs2', attr: ['W', 'WU', 'L', 'LU'], type: 4}, + {bits: 2, name: 'fmt', attr: 'D', type: 8}, + {bits: 5, name: 'funct5', attr: 'FCVT.int.D', type: 8}, +]} +.... + diff --git a/src/images/wavedrom/double-ls.adoc b/src/images/wavedrom/double-ls.adoc new file mode 100644 index 0000000..e53200d --- /dev/null +++ b/src/images/wavedrom/double-ls.adoc @@ -0,0 +1,25 @@ +//# "D" Standard Extension for Double-Precision Floating-Point, Version 2.2 +//## 13.3 Double-Precision Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'LOAD-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'width', attr: 'D', type: 8}, + {bits: 5, name: 'rs1', attr: 'base', type: 4}, + {bits: 12, name: 'imm[11:0]', attr: 'offset', type: 3}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'STORE-FP', type: 8}, + {bits: 5, name: 'imm[4:0]', attr: 'offset', type: 3}, + {bits: 3, name: 'width', attr: 'D', type: 8}, + {bits: 5, name: 'rs1', attr: 'base', type: 4}, + {bits: 5, name: 'rs2', attr: 'src', type: 4}, + {bits: 12, name: 'imm[11:5]', attr: 'offset', type: 3}, +]} +.... diff --git a/src/images/wavedrom/fcvt-sd-ds.adoc b/src/images/wavedrom/fcvt-sd-ds.adoc new file mode 100644 index 0000000..085f300 --- /dev/null +++ b/src/images/wavedrom/fcvt-sd-ds.adoc @@ -0,0 +1,16 @@ +//FCVT.S.D and FCVT.D.S + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 'rs2', attr: ['D', 'S'], type: 4}, + {bits: 2, name: 'fmt', attr: ['S','D'], type: 8}, + {bits: 5, name: 'funct5', attr: ['FCVT.S.D', 'FCVT.D.S'], type: 8}, +]} +.... + + diff --git a/src/images/wavedrom/fsjgnjnx-d.adoc b/src/images/wavedrom/fsjgnjnx-d.adoc new file mode 100644 index 0000000..5e4ca6c --- /dev/null +++ b/src/images/wavedrom/fsjgnjnx-d.adoc @@ -0,0 +1,15 @@ +//FSGNJ.D, FSGNJN.D, and FSGNJX.D + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: ['J', 'JN', 'JX'], type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'D', type: 8}, + {bits: 5, name: 'funct5', attr: 'FSGNJ', type: 8}, +]} +.... + diff --git a/src/images/wavedrom/half-ls.adoc b/src/images/wavedrom/half-ls.adoc new file mode 100644 index 0000000..41ecfaa --- /dev/null +++ b/src/images/wavedrom/half-ls.adoc @@ -0,0 +1,22 @@ +//## 15.1 Half-Precision Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'LOAD-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'width', attr: 'H', type: 8}, + {bits: 5, name: 'rs1', attr: 'base', type: 4}, + {bits: 12, name: 'imm[11:0]', attr: 'offset', type: 3}, +]})} + +${wd({reg: [ + {bits: 7, name: 'opcode', attr: 'STORE-FP', type: 8}, + {bits: 5, name: 'imm[4:0]', attr: 'offset', type: 3}, + {bits: 3, name: 'width', attr: 'H', type: 8}, + {bits: 5, name: 'rs1', attr: 'base', type: 4}, + {bits: 5, name: 'rs2', attr: 'src', type: 4}, + {bits: 12, name: 'imm[11:5]', attr: 'offset', type: 3}, +]} +.... + diff --git a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc new file mode 100644 index 0000000..37cd9e3 --- /dev/null +++ b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc @@ -0,0 +1,15 @@ +//quad-cnvrt-intch-xqqx + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: ['J', 'JN', 'JX'], type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'Q', type: 8}, + {bits: 5, name: 'funct5', attr: 'FSGNJ', type: 8}, +]} +.... + diff --git a/src/images/wavedrom/quad-cnvrt-mv.adoc b/src/images/wavedrom/quad-cnvrt-mv.adoc new file mode 100644 index 0000000..7062f18 --- /dev/null +++ b/src/images/wavedrom/quad-cnvrt-mv.adoc @@ -0,0 +1,28 @@ +//## 14.3 Quad-Precision Convert and Move Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 'rs2', attr: ['W', 'WU', 'L', 'LU'], type: 4}, + {bits: 2, name: 'fmt', attr: 'Q', type: 8}, + {bits: 5, name: 'funct5', attr: 'FCVT.int.Q', type: 8}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 'rs2', attr: ['W', 'WU', 'L', 'LU'], type: 4}, + {bits: 2, name: 'fmt', attr: 'Q', type: 8}, + {bits: 5, name: 'funct5', attr: 'FCVT.Q.int', type: 8}, +]} +.... + diff --git a/src/images/wavedrom/quad-cnvt-interchange.adoc b/src/images/wavedrom/quad-cnvt-interchange.adoc new file mode 100644 index 0000000..6820d2b --- /dev/null +++ b/src/images/wavedrom/quad-cnvt-interchange.adoc @@ -0,0 +1,16 @@ +//14 conv-mv + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 'rs2', attr: ['Q', 'S', 'Q', 'D'], type: 4}, + {bits: 2, name: 'fmt', attr: ['S','Q', 'D', 'Q'], type: 8}, + {bits: 5, name: 'funct5', attr: ['FCVT.S.Q', 'FCVT.Q.S', 'FCVT.D.Q', 'FCVT.Q.D'], type: 8}, +]} +.... + + diff --git a/src/images/wavedrom/quad-compute.adoc b/src/images/wavedrom/quad-compute.adoc new file mode 100644 index 0000000..88ddb61 --- /dev/null +++ b/src/images/wavedrom/quad-compute.adoc @@ -0,0 +1,55 @@ +//## 14.2 Quad-Precision Computational Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'Q', type: 8}, + {bits: 5, name: 'funct5', attr: ['FADD', 'FSUB', 'FMUL', 'FDIV'], type: 8}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 0, type: 8}, + {bits: 2, name: 'fmt', attr: 'Q', type: 8}, + {bits: 5, name: 'funct5', attr: 'FSQRT', type: 8}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: ['MIN', 'MAX'], type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'Q', type: 8}, + {bits: 5, name: 'funct5', attr: 'FMIN-MAX', type: 8}, +]} +.... + + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'], type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: 'RM', type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'Q', type: 8}, + {bits: 5, name: 'rs3', attr: 'src3', type: 4}, +]} +.... + diff --git a/src/images/wavedrom/quad-float-clssfy.adoc b/src/images/wavedrom/quad-float-clssfy.adoc new file mode 100644 index 0000000..8b276c8 --- /dev/null +++ b/src/images/wavedrom/quad-float-clssfy.adoc @@ -0,0 +1,15 @@ +//## 14.5 Quad-Precision Floating-Point Classify Instruction + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'rm', attr: 1, type: 8}, + {bits: 5, name: 'rs1', attr: 'src', type: 4}, + {bits: 5, name: 'rs2', attr: '0', type: 8}, + {bits: 2, name: 'fmt', attr: 'Q', type: 8}, + {bits: 5, name: 'funct5', attr: 'FCLASS', type: 8}, +]} +.... + diff --git a/src/images/wavedrom/quad-float-compare.adoc b/src/images/wavedrom/quad-float-compare.adoc new file mode 100644 index 0000000..0a4e2b7 --- /dev/null +++ b/src/images/wavedrom/quad-float-compare.adoc @@ -0,0 +1,15 @@ +//## 14.4 Quad-Precision Floating-Point Compare Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'OP-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'func3', attr: ['EQ', 'LT', 'LE'], type: 8}, + {bits: 5, name: 'rs1', attr: 'src1', type: 4}, + {bits: 5, name: 'rs2', attr: 'src2', type: 4}, + {bits: 2, name: 'fmt', attr: 'Q', type: 8}, + {bits: 5, name: 'funct5', attr: 'FCMP', type: 8}, +]} +.... + diff --git a/src/images/wavedrom/quad-ls.adoc b/src/images/wavedrom/quad-ls.adoc new file mode 100644 index 0000000..2cef49c --- /dev/null +++ b/src/images/wavedrom/quad-ls.adoc @@ -0,0 +1,25 @@ +//## 14.1 Quad-Precision Load and Store Instructions + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'LOAD-FP', type: 8}, + {bits: 5, name: 'rd', attr: 'dest', type: 2}, + {bits: 3, name: 'width', attr: 'Q', type: 8}, + {bits: 5, name: 'rs1', attr: 'base', type: 4}, + {bits: 12, name: 'imm[11:0]', attr: 'offset', type: 3}, +]} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', attr: 'STORE-FP', type: 8}, + {bits: 5, name: 'imm[4:0]', attr: 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Each figure shows the litmus test code on the left, and a visualization of one particular valid or invalid execution on the right. -include::images/graphviz/litmus_sample.adoc[] -[[litmus-sample]] -.A sample litmus test and one forbidden execution (a0=1) -image::image_placeholder.png[float+"right"] -.Key for sample litmus test -[cols="^,<,^,<",options="header",] +.Sample litmus test +graphviz::images/graphviz/litmus_sample.txt[align="center"] + +[cols="2,1"] +_Key for sample litmus test_ +[width="60%",cols="^,<,^,<",options="header",align="center"] |=== |Hart 0 | |Hart 1 | | |latexmath:[$\vdots$] | |latexmath:[$\vdots$] @@ -90,7 +90,6 @@ image::image_placeholder.png[float+"right"] | |latexmath:[$\vdots$] | |latexmath:[$\vdots$] |=== - Litmus tests are used to understand the implications of the memory model in specific concrete situations. For example, in the litmus test of <<litmus-sample>>, the final value of `a0` @@ -235,15 +234,12 @@ performing before the store. Consider the litmus test of Figure A.2. When running this program on an implementation with store buffers, it is possible to arrive at the final outcome a0=1, a1=0, a2=1, a3=0 as follows: -A store buffer forwarding litmus test (outcome permitted) - -include::images/graphviz/storebuffer.adoc[float="right"] -[[storebuffer]] .A store buffer forwarding litmus test (outcome permitted) -image::image_placeholder.png[] +graphviz::images/graphviz/litmus_sb_forward.txt[align="center"] -.A store buffer forwarding litmus test (outcome permitted) -[cols="^,<,^,<",options="header",] +[[litms_sb_forward]] +_A store buffer forwarding litmus test (outcome permitted)_ +[cols="^,<,^,<",options="header",align="center"] |=== |Hart 0 | |Hart 1 | | |li t1, 1 | |li t1, 1 @@ -312,13 +308,12 @@ Therefore, even if (b) precedes (a) in the global memory order, (b) should return the value written by (a) because (a) precedes (b) in program order. Likewise for (e) and (f). -include::images/graphviz/ppoca.adoc[] -[[ppoca]]] -.A test that highlights the behavior of store buffers -image::image_placeholder.png[] +graphviz::images/graphviz/litmus_ppoca.txt[align="center"] +.The “PPOCA” store buffer forwarding litmus test (outcome permitted) +[[litmus_ppoca]] .Key for test that highlights the behavior of store buffers -[cols="^,<,^,<",options="header",] +[cols="^,<,^,<",options="header",align="center"] |=== |Hart 0 | |Hart 1 | | |li t1, 1 | |li t1, 1 @@ -335,7 +330,7 @@ image::image_placeholder.png[] Another test that highlights the behavior of store buffers is shown in -Figure fig:litmus:ppoca[[fig:litmus:ppoca]]. In this example, (d) is +<<litmus_ppoca>>. In this example, (d) is ordered before (e) because of the control dependency, and (f) is ordered before (g) because of the address dependency. However, (e) is _not_ necessarily ordered before (f), even though (f) returns the value @@ -360,7 +355,15 @@ correct [[atomicityaxiom]] ==== Atomicity axiom -p1cm|p12cm & (for Aligned Atomics): +[NOTE] +==== +Atomicity Axiom (for Aligned Atomics): If r and w are paired load and +store operations generated by aligned LR and SC instructions in a hart +h, s is a store to byte x, and r returns a value written by s, then s must +precede w in the global memory order, and there can be no store from +a hart other than h to byte x following s and preceding w in the global +memory order. +==== The RISC-V architecture decouples the notion of atomicity from the notion of ordering. Unlike architectures such as TSO, RISC-V atomics @@ -377,19 +380,18 @@ atomic in the slightly different sense that the memory location in question will not be modified by another hart during the time the original hart holds the reservation. -{empty}(a) lr.d a0, 0(s0) (b) sd t1, 0(s0) (c) sc.d t2, 0(s0) - - +[[litmus_lrsdsc]] +.In all four (independent) instances, the store-conditional (c) is permitted but not guaranteed to succeed +[cols=3] +|==== +|(a) lr.d a0, 0(s0)|(b) sd t1, 0(s0) |(c) sc.d t2, 0(s0) -{empty}(a) lr.d a0, 0(s0) (b) sw t1, 4(s0) (c) sc.d t2, 0(s0) +|(a) lr.d a0, 0(s0) |(b) sw t1, 4(s0) |(c) sc.d t2, 0(s0) - +|(a) lr.w a0, 0(s0) |(b) sw t1, 4(s0) |(c) sc.w t2, 0(s0) -{empty}(a) lr.w a0, 0(s0) (b) sw t1, 4(s0) (c) sc.w t2, 0(s0) - - - -{empty}(a) lr.w a0, 0(s0) (b) sw t1, 4(s0) (c) sc.w t2, 8(s0) +|(a) lr.w a0, 0(s0) |(b) sw t1, 4(s0) |(c) sc.w t2, 8(s0) +|==== The atomicity axiom forbids stores from other harts from being interleaved in global memory order between an LR and the SC paired with @@ -399,13 +401,13 @@ global memory order, nor does it forbid stores from the same hart or stores to non-overlapping locations from appearing between the paired operations in either program order or in the global memory order. For example, the SC instructions in -Figure fig:litmus:lrsdsc[[fig:litmus:lrsdsc]] may (but are not +<<litmus_lrsdsc>> may (but are not guaranteed to) succeed. None of those successes would violate the atomicity axiom, because the intervening non-conditional stores are from the same hart as the paired load-reserved and store-conditional instructions. This way, a memory system that tracks memory accesses at cache line granularity (and which therefore will see the four snippets -of Figure fig:litmus:lrsdsc[[fig:litmus:lrsdsc]] as identical) will not +of <<litmus_lrsdsc>> as identical) will not be forced to fail a store-conditional instruction that happens to (falsely) share another portion of the same cache line as the memory location being held by the reservation. @@ -421,7 +423,11 @@ store may simply fall onto the same cache line. [[mm-progress]] ==== Progress -p1cm|p12cm & : +[NOTE] +==== +Progress Axiom: No memory operation may be preceded in the global +memory order by an infinite sequence of other memory operations. +==== The progress axiom ensures a minimal forward progress guarantee. It ensures that stores from one hart will eventually be made visible to @@ -443,11 +449,17 @@ the eventual visibility of all stores (or successors thereof) to all harts. [[mm-overlap]] -==== Overlapping-Address Orderings (Rules #ppo:->st[[ppo:->st]]–#ppo:amoforward[[ppo:amoforward]]) +==== Overlapping-Address Orderings (Rules 1–3) -p1cm|p12cm & Rule ppo:->st[[ppo:->st]]: + -& Rule ppo:rdw[[ppo:rdw]]: + -& Rule ppo:amoforward[[ppo:amoforward]]: + +[NOTE] +==== +Rule 1: b is a store, and a and b access overlapping memory addresses +Rule 2: a and b are loads, x is a byte read by both a and b, there is no +store to x between a and b in program order, and a and b return values +for x written by different memory operations +Rule 3: a is generated by an AMO or SC instruction, b is a load, and b +returns a value written by a +==== Same-address orderings where the latter is a store are straightforward: a load or store can never be reordered with a later store to an @@ -457,16 +469,16 @@ speculatively reordered store if the speculation turns out to be invalid, so such behavior is simply disallowed by the model. Same-address orderings from a store to a later load, on the other hand, do not need to be enforced. As discussed in -Section sec:memory:loadvalueaxiom[1.3.2], this reflects the observable +<<loadvalueaxiom>>, this reflects the observable behavior of implementations that forward values from buffered stores to later loads. Same-address load-load ordering requirements are far more subtle. The basic requirement is that a younger load must not return a value that is older than a value returned by an older load in the same hart to the -same address. This is often known as ``CoRR`` (Coherence for Read-Read -pairs), or as part of a broader ``coherence`` or ``sequential -consistency per location`` requirement. Some architectures in the past +same address. This is often known as `CoRR` (Coherence for Read-Read +pairs), or as part of a broader `coherence` or `sequential +consistency per location` requirement. Some architectures in the past have relaxed same-address load-load ordering, but in hindsight this is generally considered to complicate the programming model too much, and so RVWMO requires CoRR ordering to be enforced. However, because the @@ -475,29 +487,29 @@ rather than the ordering of the values being returned, capturing CoRR requirements in terms of the global memory order requires a bit of indirection. -m.4@m.4 +graphviz::images/graphviz/MMM.txt[] +[[loadvalueaxiom]] +.A sample litmus test and one forbidden execution (a0=1) -` ` [cols="^,<,^,<",options="header",] |=== |Hart 0 | |Hart 1 | -| |li t1, 1 | |li t2, 2 -|(a) |sw t1,0(s0) |(d) |lw a0,0(s1) -|(b) |fence w, w |(e) |sw t2,0(s1) -|(c) |sw t1,0(s1) |(f) |lw a1,0(s1) +| |li t1, 1 | |li t2, 2 +|(a) |sw t1,0(s0) |(d) |lw a0,0(s1) +|(b) |fence w, w |(e) |sw t2,0(s1) +|(c) |sw t1,0(s1) |(f) |lw a1,0(s1) | | |(g) |xor t3,a1,a1 | | |(h) |add s0,s0,t3 -| | |(i) |lw a2,0(s0) +| | |(i) |lw a2,0(s0) |Outcome: `a0=1`, `a1=2`, `a2=0` | | | |=== -& Consider the litmus test of -Figure fig:litmus:frirfi[[fig:litmus:frirfi]], which is one particular -instance of the more general ``fri-rfi`` pattern. The term ``fri-rfi`` -refers to the sequence (d), (e), (f): (d) ``from-reads`` (i.e., reads +<<frirfi>>, which is one particular +instance of the more general `fri-rfi` pattern. The term `fri-rfi` +refers to the sequence (d), (e), (f): (d) `from-reads` (i.e., reads from an earlier write than) (e) which is the same hart, and (f) reads from (e) which is in the same hart. @@ -534,20 +546,20 @@ m.4@m.6 [cols="^,<,^,<",options="header",] |=== |Hart 0 | |Hart 1 | -| |li t1, 1 |(d) |lw a0,0(s1) +| |li t1, 1 |(d) |lw a0,0(s1) |(a) |sw t1,0(s0) |(e) |xor t2,a0,a0 |(b) |fence w, w |(f) |add s4,s2,t2 -|(c) |sw t1,0(s1) |(g) |lw a1,0(s4) -| | |(h) |lw a2,0(s2) +|(c) |sw t1,0(s1) |(g) |lw a1,0(s4) +| | |(h) |lw a2,0(s2) | | |(i) |xor t3,a2,a2 | | |(j) |add s0,s0,t3 -| | |(k) |lw a3,0(s0) +| | |(k) |lw a3,0(s0) |Outcome: `a0=1`, `a1=v`, `a2=v`, `a3=0` | | | |=== & -Consider the litmus test of Figure fig:litmus:rsw[[fig:litmus:rsw]]. +Consider the litmus test of <<litmus-rsw>>. The outcome `a0=1`, `a1=v`, `a2=v`, `a3=0` (where latexmath:[$v$] is some value written by another hart) can be observed by allowing (g) and (h) to be reordered. This might be done speculatively, and the @@ -559,24 +571,24 @@ same store anyway, (g) and (h) can be legally reordered. The global memory order corresponding to this execution would be (h),(k),(a),(c),(d),(g). -Executions of the test in Figure fig:litmus:rsw[[fig:litmus:rsw]] in +Executions of the test in <<litmus-rsw>> in which `a1` does not equal `a2` do in fact require that (g) appears before (h) in the global memory order. Allowing (h) to appear before (g) in the global memory order would in that case result in a violation of CoRR, because then (h) would return an older value than that returned by -(g). Therefore, PPO rule ppo:rdw[[ppo:rdw]] forbids this CoRR violation -from occurring. As such, PPO rule ppo:rdw[[ppo:rdw]] strikes a careful +(g). Therefore, PPO rule ppo:rdw[[ppo:rdw]] forbids this CoRR violation +from occurring. As such, PPO rule ppo:rdw[[ppo:rdw]] strikes a careful balance between enforcing CoRR in all cases while simultaneously being weak enough to permit `RSW` and `fri-rfi` patterns that commonly appear in real microarchitectures. There is one more overlapping-address rule: PPO -rule ppo:amoforward[[ppo:amoforward]] simply states that a value cannot +rule ppo:amoforward[[ppo:amoforward]] simply states that a value cannot be returned from an AMO or SC to a subsequent load until the AMO or SC has (in the case of the SC, successfully) performed globally. This follows somewhat naturally from the conceptual view that both AMOs and SC instructions are meant to be performed atomically in memory. However, -notably, PPO rule ppo:amoforward[[ppo:amoforward]] states that hardware +notably, PPO rule ppo:amoforward[[ppo:amoforward]] states that hardware may not even non-speculatively forward the value being stored by an AMOSWAP to a subsequent load, even though for AMOSWAP that store value is not actually semantically dependent on the previous value in memory, @@ -598,10 +610,10 @@ rules apply to each of the component memory accesses independently. p1cm|p12cm & Rule ppo:fence[[ppo:fence]]: By default, the FENCE instruction ensures that all memory accesses from -instructions preceding the fence in program order (the ``predecessor -set``) appear earlier in the global memory order than memory accesses +instructions preceding the fence in program order (the `predecessor +set`) appear earlier in the global memory order than memory accesses from instructions appearing after the fence in program order (the -``successor set``). However, fences can optionally further restrict the +`successor set`). However, fences can optionally further restrict the predecessor set and/or the successor set to a smaller set of memory accesses in order to provide some speedup. Specifically, fences have PR, PW, SR, and SW bits which restrict the predecessor and/or successor @@ -611,7 +623,7 @@ sets. The predecessor set includes loads (resp.stores) if and only if PR The FENCE encoding currently has nine non-trivial combinations of the four bits PR, PW, SR, and SW, plus one extra encoding FENCE.TSO which -facilitates mapping of ``acquire+release`` or RVTSO semantics. The +facilitates mapping of `acquire+release` or RVTSO semantics. The remaining seven combinations have empty predecessor and/or successor sets and hence are no-ops. Of the ten non-trivial options, only six are commonly used in practice: @@ -630,11 +642,11 @@ memory model. Finally, we note that since RISC-V uses a multi-copy atomic memory model, programmers can reason about fences bits in a thread-local -manner. There is no complex notion of ``fence cumulativity`` as found in +manner. There is no complex notion of `fence cumulativity` as found in memory models that are not multi-copy atomic. [[sec:memory:acqrel]] -==== Explicit Synchronization (Rules #ppo:acquire[[ppo:acquire]]–#ppo:pair[[ppo:pair]]) +==== Explicit Synchronization (Rules #ppo:acquire[[ppo:acquire]]–#ppo:pair[[ppo:pair]]) p1cm|p12cm & Rule ppo:acquire[[ppo:acquire]]: + & Rule ppo:release[[ppo:release]]: + @@ -648,7 +660,7 @@ ensures, for example, that all loads and stores inside the critical section are up to date with respect to the synchronization variable being used to protect it. Acquire ordering can be enforced in one of two ways: with an acquire annotation, which enforces ordering with respect -to just the synchronization variable itself, or with a FENCE R,RW, which +to just the synchronization variable itself, or with a FENCE R,RW, which enforces ordering with respect to all previous loads. .... @@ -672,8 +684,8 @@ Because this example uses _aq_, the loads and stores in the critical section are guaranteed to appear in the global memory order after the AMOSWAP used to acquire the lock. However, assuming `a0`, `a1`, and `a2` point to different memory locations, the loads and stores in the -critical section may or may not appear after the ``Arbitrary unrelated -load`` at the beginning of the example in the global memory order. +critical section may or may not appear after the `Arbitrary unrelated +load` at the beginning of the example in the global memory order. .... sd x1, (a1) # Arbitrary unrelated store @@ -693,16 +705,16 @@ load`` at the beginning of the example in the global memory order. .... Now, consider the alternative in -Figure fig:litmus:spinlock_fences[[fig:litmus:spinlock_fences]]. In +<<spinlock_fences>>. In this case, even though the AMOSWAP does not enforce ordering with an _aq_ bit, the fence nevertheless enforces that the acquire AMOSWAP appears earlier in the global memory order than all loads and stores in the critical section. Note, however, that in this case, the fence also -enforces additional orderings: it also requires that the ``Arbitrary -unrelated load`` at the start of the program appears earlier in the +enforces additional orderings: it also requires that the `Arbitrary +unrelated load` at the start of the program appears earlier in the global memory order than the loads and stores of the critical section. (This particular fence does not, however, enforce any ordering with -respect to the ``Arbitrary unrelated store`` at the start of the +respect to the `Arbitrary unrelated store` at the start of the snippet.) In this way, fence-enforced orderings are slightly coarser than orderings enforced by _.aq_. @@ -713,39 +725,37 @@ release operation in the global memory order. This ensures, for example, that memory accesses in a critical section appear before the lock-releasing store in the global memory order. Just as for acquire semantics, release semantics can be enforced using release annotations -or with a FENCE RW,W operation. Using the same examples, the ordering -between the loads and stores in the critical section and the ``Arbitrary -unrelated store`` at the end of the code snippet is enforced only by the -FENCE RW,W in -Figure #fig:litmus:spinlock_fences[[fig:litmus:spinlock_fences]], not by -the _rl_ in -Figure #fig:litmus:spinlock_atomics[[fig:litmus:spinlock_atomics]]. +or with a FENCE RW,W operation. Using the same examples, the ordering +between the loads and stores in the critical section and the `Arbitrary +unrelated store` at the end of the code snippet is enforced only by the +FENCE RW,W in <<spinlock_fences>>, not by +the _rl_ in <<spinlock_atomics>>. With RCpc annotations alone, store-release-to-load-acquire ordering is not enforced. This facilitates the porting of code written under the TSO and/or RCpc memory models. To enforce store-release-to-load-acquire ordering, the code must use store-release-RCsc and load-acquire-RCsc -operations so that PPO rule #ppo:rcsc[[ppo:rcsc]] applies. RCpc alone is +operations so that PPO rule ppo:rcsc[[ppo:rcsc]] applies. RCpc alone is sufficient for many use cases in C/C++ but is insufficient for many other use cases in C/C++, Java, and Linux, to name just a few examples; -see Section #sec:memory:porting[1.5] for details. +see <<memory-porting>> for details. -PPO rule #ppo:pair[[ppo:pair]] indicates that an SC must appear after +PPO rule ppo:pair[[ppo:pair]] indicates that an SC must appear after its paired LR in the global memory order. This will follow naturally from the common use of LR/SC to perform an atomic read-modify-write operation due to the inherent data dependency. However, PPO -rule #ppo:pair[[ppo:pair]] also applies even when the value being stored +rule ppo:pair[[ppo:pair]] also applies even when the value being stored does not syntactically depend on the value returned by the paired LR. Lastly, we note that just as with fences, programmers need not worry -about ``cumulativity`` when analyzing ordering annotations. +about `cumulativity` when analyzing ordering annotations. [[sec:memory:dependencies]] -==== Syntactic Dependencies (Rules #ppo:addr[[ppo:addr]]–#ppo:ctrl[[ppo:ctrl]]) +==== Syntactic Dependencies (Rules ppo:addr[[ppo:addr]]–#ppo:ctrl[[ppo:ctrl]]) -p1cm|p12cm & Rule #ppo:addr[[ppo:addr]]: + -& Rule #ppo:data[[ppo:data]]: + -& Rule #ppo:ctrl[[ppo:ctrl]]: + +[[ppo-addr]] +& Rule ppo:data[[ppo:data]]: + +& Rule ppo:ctrl[[ppo:ctrl]]: + Dependencies from a load to a later memory operation in the same hart are respected by the RVWMO memory model. The Alpha memory model was @@ -779,7 +789,7 @@ The notion of accumulating into a destination register rather than writing into it reflects the behavior of CSRs such as `fflags`. In particular, an accumulation into a register does not clobber any previous writes or accumulations into the same register. For example, in -Figure #fig:litmus:fflags[[fig:litmus:fflags]], (c) has a syntactic +<<fflags>>, (c) has a syntactic dependency on both (a) and (b). Like other modern memory models, the RVWMO memory model uses syntactic @@ -787,7 +797,7 @@ rather than semantic dependencies. In other words, this definition depends on the identities of the registers being accessed by different instructions, not the actual contents of those registers. This means that an address, control, or data dependency must be enforced even if -the calculation could seemingly be ``optimized away``. This choice +the calculation could seemingly be `optimized away`. This choice ensures that RVWMO remains compatible with code that uses these false syntactic dependencies as a lightweight ordering mechanism. @@ -796,7 +806,7 @@ ld a1,0(s0) xor a2,a1,a1 add s1,s1,a2 ld a5,0(s1) For example, there is a syntactic address dependency from the memory operation generated by the first instruction to the memory operation generated by the last instruction in -Figure #fig:litmus:address[[fig:litmus:address]], even though `a1` XOR +<<address>>, even though `a1` XOR `a1` is zero and hence has no effect on the address accessed by the second load. @@ -806,7 +816,7 @@ to the specific two instructions in question. Other non-dependent instructions may be freely reordered by aggressive implementations. One alternative would be to use a load-acquire, but this would enforce ordering for the first load with respect to _all_ subsequent -instructions. Another would be to use a FENCE R,R, but this would +instructions. Another would be to use a FENCE R,R, but this would include all previous and all subsequent loads, making this option more expensive. @@ -815,14 +825,14 @@ lw x1,0(x2) bne x1,x0,next sw x3,0(x4) next: sw x5,0(x6) Control dependencies behave differently from address and data dependencies in the sense that a control dependency always extends to all instructions following the original target in program order. -Consider Figure #fig:litmus:control1[[fig:litmus:control1]]: the +Consider <<control1>> the instruction at `next` will always execute, but the memory operation generated by that last instruction nevertheless still has a control dependency from the memory operation generated by the first instruction. lw x1,0(x2) bne x1,x0,next next: sw x3,0(x4) -Likewise, consider Figure #fig:litmus:control2[[fig:litmus:control2]]. +Likewise, consider <<control2>>. Even though both branch outcomes have the same target, there is still a control dependency from the memory operation generated by the first instruction in this snippet to the memory operation generated by the @@ -831,14 +841,14 @@ stronger than what might be seen in other contexts (e.g., C++), but it conforms with standard definitions of control dependencies in the literature. -Notably, PPO rules #ppo:addr[[ppo:addr]]–#ppo:ctrl[[ppo:ctrl]] are also +Notably, PPO rules ppo:addr[[ppo:addr]]–#ppo:ctrl[[ppo:ctrl]] are also intentionally designed to respect dependencies that originate from the output of a successful store-conditional instruction. Typically, an SC instruction will be followed by a conditional branch checking whether the outcome was successful; this implies that there will be a control dependency from the store operation generated by the SC instruction to any memory operations following the branch. PPO -rule #ppo:ctrl[[ppo:ctrl]] in turn implies that any subsequent store +rule ppo:ctrl[[ppo:ctrl]] in turn implies that any subsequent store operations will appear later in the global memory order than the store operation generated by the SC. However, since control, address, and data dependencies are defined over memory operations, and since an @@ -869,7 +879,7 @@ m.4m0.05m.4 In addition, the choice to respect dependencies originating at store-conditional instructions ensures that certain out-of-thin-air-like behaviors will be prevented. Consider -Figure #fig:litmus:successdeps[[fig:litmus:successdeps]]. Suppose a +<<successdeps>>. Suppose a hypothetical implementation could occasionally make some early guarantee that a store-conditional operation will succeed. In this case, (c) could return 0 to `a2` early (before actually executing), allowing the @@ -883,18 +893,19 @@ instructions. We also note that syntactic dependencies between instructions only have any force when they take the form of a syntactic address, control, and/or data dependency. For example: a syntactic dependency between two -``F`` instructions via one of the ``accumulating CSRs`` in -Section #sec:source-dest-regs[[sec:source-dest-regs]] does _not_ imply -that the two ``F`` instructions must be executed in order. Such a +`F` instructions via one of the `accumulating CSRs` in +<<source-dest-regs>> does _not_ imply +that the two `F` instructions must be executed in order. Such a dependency would only serve to ultimately set up later a dependency from -both ``F`` instructions to a later CSR instruction accessing the CSR +both `F` instructions to a later CSR instruction accessing the CSR flag in question. -[[sec:memory:ppopipeline]] -==== Pipeline Dependencies (Rules #ppo:addrdatarfi[[ppo:addrdatarfi]]–#ppo:addrpo[[ppo:addrpo]]) +[[memory-ppopipeline]] +==== Pipeline Dependencies (Rules ppo:addrdatarfi[[ppo:addrdatarfi]]–ppo:addrpo[[ppo:addrpo]]) -p1cm|p12cm & Rule #ppo:addrdatarfi[[ppo:addrdatarfi]]: + -& Rule #ppo:addrpo[[ppo:addrpo]]: + +[[addrdatarfi]] +p1cm|p12cm & Rule ppo:addrdatarfi: + +& Rule ppo:addrpo[[ppo:addrpo]]: + m.4m.05m.4 @@ -914,12 +925,12 @@ m.4m.05m.4 & & -PPO rules #ppo:addrdatarfi[[ppo:addrdatarfi]] and -#ppo:addrpo[[ppo:addrpo]] reflect behaviors of almost all real processor -pipeline implementations. Rule #ppo:addrdatarfi[[ppo:addrdatarfi]] +PPO rules ppo:addrdatarfi[[ppo:addrdatarfi]] and +ppo:addrpo[[ppo:addrpo]] reflect behaviors of almost all real processor +pipeline implementations. Rule ppo:addrdatarfi states that a load cannot forward from a store until the address and data for that store are known. Consider -Figure #fig:litmus:addrdatarfi[[fig:litmus:addrdatarfi]]: (f) cannot be +<<addrdatarfi>> (f) cannot be executed until the data for (e) has been resolved, because (f) must return the value written by (e) (or by something even later in the global memory order), and the old value must not be clobbered by the @@ -930,6 +941,7 @@ m.4m.05m.4 ` ` +[[addrdatarfi]] [cols="^,<,^,<",options="header",] |=== |Hart 0 | |Hart 1 | @@ -947,12 +959,12 @@ m.4m.05m.4 & & If there were another store to the same address in between (e) and (f), -as in Figure #fig:litmus:addrdatarfi_no[[fig:litmus:addrdatarfi_no]], +as in <<litmus:addrdatarfi_no>>, then (f) would no longer be dependent on the data of (e) being resolved, and hence the dependency of (f) on (d), which produces the data for (e), would be broken. -Rule #ppo:addrpo[[ppo:addrpo]] makes a similar observation to the +Rule ppo:addrpo[[ppo:addrpo]] makes a similar observation to the previous rule: a store cannot be performed at memory until all previous loads that might access the same address have themselves been performed. Such a load must appear to execute before the store, but it cannot do so @@ -960,8 +972,8 @@ if the store were to overwrite the value in memory before the load had a chance to read the old value. Likewise, a store generally cannot be performed until it is known that preceding instructions will not cause an exception due to failed address resolution, and in this sense, -rule #ppo:addrpo[[ppo:addrpo]] can be seen as somewhat of a special case -of rule #ppo:ctrl[[ppo:ctrl]]. +rule ppo:addrpo[[ppo:addrpo]] can be seen as somewhat of a special case +of rule ppo:ctrl[[ppo:ctrl]]. m.4m.05m.4 ` ` @@ -977,7 +989,7 @@ m.4m.05m.4 ` ` & & -Consider Figure #fig:litmus:addrpo[[fig:litmus:addrpo]]: (f) cannot be +Consider <<addrpo>> (f) cannot be executed until the address for (e) is resolved, because it may turn out that the addresses match; i.e., that `a1=s0`. Therefore, (f) cannot be sent to memory before (d) has executed and confirmed whether the @@ -988,7 +1000,7 @@ addresses do indeed overlap. RVWMO does not currently attempt to formally describe how FENCE.I, SFENCE.VMA, I/O fences, and PMAs behave. All of these behaviors will be described by future formalizations. In the meantime, the behavior of -FENCE.I is described in Chapter #chap:zifencei[[chap:zifencei]], the +FENCE.I is described in <<zifencei>>, the behavior of SFENCE.VMA is described in the RISC-V Instruction Set Privileged Architecture Manual, and the behavior of I/O fences and the effects of PMAs are described below. @@ -1029,7 +1041,7 @@ legal. This distinction does not affect the memory model. For I/O, the load value axiom and atomicity axiom in general do not apply, as both reads and writes might have device-specific side effects -and may return values other than the value ``written`` by the most +and may return values other than the value `written` by the most recent store to the same address. Nevertheless, the following preserved program order rules still generally apply for accesses to I/O memory: memory access latexmath:[$a$] precedes memory access latexmath:[$b$] in @@ -1037,7 +1049,7 @@ global memory order if latexmath:[$a$] precedes latexmath:[$b$] in program order and one or more of the following holds: . latexmath:[$a$] precedes latexmath:[$b$] in preserved program order as -defined in Chapter #ch:memorymodel[[ch:memorymodel]], with the exception +defined in <<memorymodel>>, with the exception that acquire and release ordering annotations apply only from one memory operation to another memory operation and from one I/O operation to another I/O operation, but not from a memory operation to an I/O nor @@ -1057,7 +1069,7 @@ operations and I/O operations in its predecessor and successor sets. To enforce ordering between I/O operations and main memory operations, code must use a FENCE with PI, PO, SI, and/or SO, plus PR, PW, SR, and/or SW. For example, to enforce ordering between a write to main memory and an -I/O write to a device register, a FENCE W,O or stronger is needed. +I/O write to a device register, a FENCE W,O or stronger is needed. sd t0, 0(a0) fence w,o sd a0, 0(a1) @@ -1065,7 +1077,7 @@ When a fence is in fact used, implementations must assume that the device may attempt to access memory immediately after receiving the MMIO signal, and subsequent memory accesses from that device to memory must observe the effects of all accesses ordered prior to that MMIO -operation. In other words, in Figure #fig:litmus:wo[[fig:litmus:wo]], +operation. In other words, in <<wo>>, suppose `0(a0)` is in main memory and `0(a1)` is the address of a device register in I/O memory. If the device accesses `0(a0)` upon receiving the MMIO write, then that load must conceptually appear after the first @@ -1079,8 +1091,8 @@ distinguish between these options; it simply provides an implementation-agnostic mechanism to specify the orderings that must be enforced. -Many architectures include separate notions of ``ordering`` and -``completion`` fences, especially as it relates to I/O (as opposed to +Many architectures include separate notions of `ordering` and +`completion` fences, especially as it relates to I/O (as opposed to regular main memory). Ordering fences simply ensure that memory operations stay in order, while completion fences ensure that predecessor accesses have all completed before any successors are made @@ -1117,11 +1129,11 @@ those external devices and buses. [cols="<,<",options="header",] |=== |x86/TSO Operation |RVWMO Mapping -|Load |`l{b|h|w|d}; fence r,rw ` -|Store |`fence rw,w; s{b|h|w|d} ` -|Atomic RMW |`amo<op>.{w|d}.aqrl OR ` -| |`loop:lr.{w|d}.aq; <op>; sc.{w|d}.aqrl; bnez loop ` -|Fence |`fence rw,rw ` +|Load | `l{b|h|w|d}; fence r,rw` +|Store |`fence rw,w; s{b|h|w|d}` +|Atomic RMW |`amo<op>.{w|d}.aqrl OR` +| |`loop:lr.{w|d}.aq; <op>; sc.{w|d}.aqrl; bnez loop` +|Fence |`fence rw,rw` |=== <<somappings>> provides a mapping from TSO memory @@ -1129,8 +1141,8 @@ operations onto RISC-V memory instructions. Normal x86 loads and stores are all inherently acquire-RCpc and release-RCpc operations: TSO enforces all load-load, load-store, and store-store ordering by default. Therefore, under RVWMO, all TSO loads must be mapped onto a load -followed by FENCE R,RW, and all TSO stores must be mapped onto -FENCE RW,W followed by a store. TSO atomic read-modify-writes and x86 +followed by FENCE R,RW, and all TSO stores must be mapped onto +FENCE RW,W followed by a store. TSO atomic read-modify-writes and x86 instructions using the LOCK prefix are fully ordered and can be implemented either via an AMO with both _aq_ and _rl_ set, or via an LR with _aq_ set, the arithmetic operation in question, an SC with both @@ -1140,7 +1152,7 @@ condition. In the latter case, the _rl_ annotation on the LR turns out Alternatives to <<somappings>> are also possible. A TSO store can be mapped onto AMOSWAP with _rl_ set. However, since RVWMO PPO -Rule #ppo:amoforward[[ppo:amoforward]] forbids forwarding of values from +Rule ppo:amoforward [[amoforward]] forbids forwarding of values from AMOs to subsequent loads, the use of AMOSWAP for stores may negatively affect performance. A TSO load can be mapped using LR with _aq_ set: all such LR instructions will be unpaired, but that fact in and of itself @@ -1153,18 +1165,18 @@ reservation mechanism than was originally intended. [cols="<,<",options="header",] |=== |Power Operation |RVWMO Mapping -|Load |`l{b|h|w|d} ` -|Load-Reserve |`lr.{w|d} ` -|Store |`s{b|h|w|d} ` -|Store-Conditional |`sc.{w|d} ` -|`lwsync ` |`fence.tso ` -|`sync ` |`fence rw,rw ` -|`isync ` |`fence.i; fence r,r ` +|Load |`l{b|h|w|d}` +|Load-Reserve |`lr.{w|d}` +|Store |`s{b|h|w|d}` +|Store-Conditional |`sc.{w|d}` +|`lwsync` |`fence.tso` +|`sync` |`fence rw,rw` +|`isync` |`fence.i; fence r,r` |=== <<powermappings>> provides a mapping from Power memory operations onto RISC-V memory instructions. Power ISYNC maps on RISC-V -to a FENCE.I followed by a FENCE R,R; the latter fence is needed because +to a FENCE.I followed by a FENCE R,R; the latter fence is needed because ISYNC is used to define a `control+control fence` dependency that is not present in RVWMO. @@ -1173,18 +1185,18 @@ not present in RVWMO. [cols="<,<",options="header",] |=== |ARM Operation |RVWMO Mapping -|Load |`l{b|h|w|d} ` -|Load-Acquire |`fence rw, rw; l{b|h|w|d}; fence r,rw ` -|Load-Exclusive |`lr.{w|d} ` -|Load-Acquire-Exclusive |`lr.{w|d}.aqrl ` -|Store |`s{b|h|w|d} ` -|Store-Release |`fence rw,w; s{b|h|w|d} ` -|Store-Exclusive |`sc.{w|d} ` -|Store-Release-Exclusive |`sc.{w|d}.rl ` -|`dmb ` |`fence rw,rw ` -|`dmb.ld ` |`fence r,rw ` -|`dmb.st ` |`fence w,w ` -|`isb ` |`fence.i; fence r,r ` +|Load |`l{b|h|w|d}` +|Load-Acquire |`fence rw, rw; l{b|h|w|d}; fence r,rw` +|Load-Exclusive |`lr.{w|d}` +|Load-Acquire-Exclusive |`lr.{w|d}.aqrl` +|Store |`s{b|h|w|d}` +|Store-Release |`fence rw,w; s{b|h|w|d}` +|Store-Exclusive |`sc.{w|d}` +|Store-Release-Exclusive |`sc.{w|d}.rl` +|`dmb` |`fence rw,rw` +|`dmb.ld` |`fence r,rw` +|`dmb.st` |`fence w,w` +|`isb` |`fence.i; fence r,r` |=== <<armmappings>> provides a mapping from ARM memory @@ -1192,75 +1204,77 @@ operations onto RISC-V memory instructions. Since RISC-V does not currently have plain load and store opcodes with _aq_ or _rl_ annotations, ARM load-acquire and store-release operations should be mapped using fences instead. Furthermore, in order to enforce -store-release-to-load-acquire ordering, there must be a FENCE RW,RW -between the store-release and load-acquire; Table #tab:armmappings[1.4] +store-release-to-load-acquire ordering, there must be a FENCE RW,RW +between the store-release and load-acquire; Table tab:armmappings[1.4] enforces this by always placing the fence in front of each acquire operation. ARM load-exclusive and store-exclusive instructions can likewise map onto their RISC-V LR and SC equivalents, but instead of -placing a FENCE RW,RW in front of an LR with _aq_ set, we simply also +placing a FENCE RW,RW in front of an LR with _aq_ set, we simply also set _rl_ instead. ARM ISB maps on RISC-V to FENCE.I followed by -FENCE R,R similarly to how ISYNC maps for Power. +FENCE R,R similarly to how ISYNC maps for Power. [[linuxmappings]] .Mappings from Linux memory primitives to RISC-V primitives. [cols="<,<",options="header",] |=== |Linux Operation |RVWMO Mapping -|`smp_mb() ` |`fence rw,rw ` -|`smp_rmb() ` |`fence r,r ` +|`smp_mb()` |`fence rw,rw` + +|`smp_rmb()` |`fence r,r` -|`smp_wmb() ` |`fence w,w ` +|`smp_wmb()` |`fence w,w` -|`dma_rmb() ` |`fence r,r ` +|`dma_rmb()` |`fence r,r` -|`dma_wmb() ` |`fence w,w ` +|`dma_wmb()` |`fence w,w` -|`mb() ` |`fence iorw,iorw ` +|`mb()` |`fence iorw,iorw` -|`rmb() ` |`fence ri,ri ` +|`rmb()` |`fence ri,ri` -|`wmb() ` |`fence wo,wo ` +|`wmb()` |`fence wo,wo` -|`smp_load_acquire() ` |`l{b|h|w|d}; fence r,rw ` +|`smp_load_acquire()` |`l{b|h|w|d}; fence r,rw` -|`smp_store_release() ` |`fence.tso; s{b|h|w|d} ` +|`smp_store_release()` |`fence.tso; s{b|h|w|d}` |Linux Construct |RVWMO AMO Mapping -|`atomic_<op>_relaxed ` |`amo<op>.{w|d} ` +|`atomic_ < op >_relaxed` |`amo < op >.{w|d}` -|`atomic_<op>_acquire ` |`amo<op>.{w|d}.aq ` +|`atomic_ <op >_acquire` |`amo <op >.{w|d}.aq` -|`atomic_<op>_release ` |`amo<op>.{w|d}.rl ` +|`atomic_ <op >_release` |`amo <op >.{w|d}.rl` -|`atomic_<op> ` |`amo<op>.{w|d}.aqrl ` +|`atomic_ <op >_` |`amo <op >.{w|d}.aqrl` |Linux Construct |RVWMO LR/SC Mapping -|`atomic_<op>_relaxed ` |`loop:lr.{w|d}; <op>; sc.{w|d}; bnez loop ` +|`atomic_ <op >_relaxed` |`loop:lr.{w|d}; <op& #62;; sc.{w|d}; bnez loop` -|`atomic_<op>_acquire ` |`loop:lr.{w|d}.aq; <op>; sc.{w|d}; bnez loop ` +|`atomic_ <op >_acquire` |`loop:lr.{w|d}.aq; <op >; sc.{w|d}; bnez loop` -|`atomic_<op>_release` -|`loop:lr.{w|d}; <op>; sc.{w|d}.aqrl^*; bnez loop OR ` +|`atomic_ <op >_release` |`loop:lr.{w|d}; <op >; sc.{w|d}.aqrl^*; bnez loop OR` -| |`fence.tso; loop:lr.{w|d}; <op>; sc.{w|d}^*; bnez loop ` +| |`fence.tso; loop:lr.{w|d}; <op >; sc.{w|d}^*; bnez loop` + +|`atomic_ <op >_` |`loop:lr.{w|d}.aq;` `< op > ; sc.{w|d}.aqrl; bnez loop` -|`atomic_<op> ` |`loop:lr.{w|d}.aq; <op>; sc.{w|d}.aqrl; bnez loop ` |=== -With regosrds to <<linuxmappings>>, other + +With regards to <<linuxmappings>>, other constructs (such as spinlocks) should follow accordingly. Platforms or devices with non-coherent DMA may need additional synchronization (such as cache flush or invalidate mechanisms); currently any such extra synchronization will be device-specific. -Table #tab:linuxmappings[1.5] provides a mapping of Linux memory +Table tab:linuxmappings[1.5] provides a mapping of Linux memory ordering macros onto RISC-V memory instructions. The Linux fences -`dma_rmb()` and `dma_wmb()` map onto FENCE R,R and FENCE W,W, +`dma_rmb()` and `dma_wmb()` map onto FENCE R,R and FENCE W,W, respectively, since the RISC-V Unix Platform requires coherent DMA, but -would be mapped onto FENCE RI,RI and FENCE WO,WO, respectively, on a +would be mapped onto FENCE RI,RI and FENCE WO,WO, respectively, on a platform with non-coherent DMA. Platforms with non-coherent DMA may also require a mechanism by which cache lines can be flushed and/or invalidated. Such mechanisms will be device-specific and/or standardized @@ -1274,22 +1288,22 @@ is actively debating whether to require load-load, load-store, and store-store orderings between accesses in one critical section and accesses in a subsequent critical section in the same hart and protected by the same synchronization object. Not all combinations of -FENCE RW,W/FENCE R,RW mappings with _aq_/_rl_ mappings combine to +FENCE RW,W/FENCE R,RW mappings with _aq_/_rl_ mappings combine to provide such orderings. There are a few ways around this problem, including: -. Always use FENCE RW,W/FENCE R,RW, and never use _aq_/_rl_. This +. Always use FENCE RW,W/FENCE R,RW, and never use _aq_/_rl_. This suffices but is undesirable, as it defeats the purpose of the _aq_/_rl_ modifiers. -. Always use _aq_/_rl_, and never use FENCE RW,W/FENCE R,RW. This does +. Always use _aq_/_rl_, and never use FENCE RW,W/FENCE R,RW. This does not currently work due to the lack of load and store opcodes with _aq_ and _rl_ modifiers. . Strengthen the mappings of release operations such that they would enforce sufficient orderings in the presence of either type of acquire mapping. This is the currently recommended solution, and the one shown -in Table #tab:linuxmappings[1.5]. +in Table #tab:linuxmappings[1.5]. + - RVWMO Mapping: (a) lw a0, 0(s0) (b) fence.tso // vs. fence rw,w (c) sd x0,0(s1) ... loop: (d) amoswap.d.aq a1,t1,0(s1) bnez a1,loop (e) lw @@ -1297,8 +1311,8 @@ a2,0(s2) For example, the critical section ordering rule currently being debated by the Linux community would require (a) to be ordered before (e) in -Figure #fig:litmus:lkmm_ll[[fig:litmus:lkmm_ll]]. If that will indeed be -required, then it would be insufficient for (b) to map as FENCE RW,W. +Figure #fig:litmus:lkmm_ll[[fig:litmus:lkmm_ll]]. If that will indeed be +required, then it would be insufficient for (b) to map as FENCE RW,W. That said, these mappings are subject to change as the Linux Kernel Memory Model evolves. @@ -1307,67 +1321,67 @@ Memory Model evolves. [cols="<,<",options="header",] |=== |C/C++ Construct |RVWMO Mapping -|Non-atomic load |`l{b|h|w|d} ` +|Non-atomic load |`l{b|h|w|d}` -|`atomic_load(memory_order_relaxed) ` |`l{b|h|w|d} ` +|`atomic_load(memory_order_relaxed)` |`l{b|h|w|d}` -|`atomic_load(memory_order_acquire) ` |`l{b|h|w|d}; fence r,rw ` +|`atomic_load(memory_order_acquire)` |`l{b|h|w|d}; fence r,rw` -|`atomic_load(memory_order_seq_cst) ` -|`fence rw,rw; l{b|h|w|d}; fence r,rw ` +|`atomic_load(memory_order_seq_cst)` +|`fence rw,rw; l{b|h|w|d}; fence r,rw` -|Non-atomic store |`s{b|h|w|d} ` +|Non-atomic store |`s{b|h|w|d}` -|`atomic_store(memory_order_relaxed) ` |`s{b|h|w|d} ` +|`atomic_store(memory_order_relaxed)` |`s{b|h|w|d}` -|`atomic_store(memory_order_release) ` |`fence rw,w; s{b|h|w|d} ` +|`atomic_store(memory_order_release)` |`fence rw,w; s{b|h|w|d}` -|`atomic_store(memory_order_seq_cst) ` |`fence rw,w; s{b|h|w|d} ` +|`atomic_store(memory_order_seq_cst)` |`fence rw,w; s{b|h|w|d}` -|`atomic_thread_fence(memory_order_acquire) ` |`fence r,rw ` +|`atomic_thread_fence(memory_order_acquire)` |`fence r,rw` -|`atomic_thread_fence(memory_order_release) ` |`fence rw,w ` +|`atomic_thread_fence(memory_order_release)` |`fence rw,w` -|`atomic_thread_fence(memory_order_acq_rel) ` |`fence.tso` +|`atomic_thread_fence(memory_order_acq_rel)` |`fence.tso` -|`atomic_thread_fence(memory_order_seq_cst) ` |`fence rw,rw ` +|`atomic_thread_fence(memory_order_seq_cst)` |`fence rw,rw` |C/C++ Construct |RVWMO AMO Mapping -|`atomic_<op>(memory_order_relaxed) ` |`amo<op>.{w|d} ` +|`atomic_<op>(memory_order_relaxed)` |`amo<op>.{w|d}` -|`atomic_<op>(memory_order_acquire) ` |`amo<op>.{w|d}.aq ` +|`atomic_<op>(memory_order_acquire)` |`amo<op>.{w|d}.aq` -|`atomic_<op>(memory_order_release) ` |`amo<op>.{w|d}.rl ` +|`atomic_<op>(memory_order_release)` |`amo<op>.{w|d}.rl` -|`atomic_<op>(memory_order_acq_rel) ` |`amo<op>.{w|d}.aqrl ` +|`atomic_<op>(memory_order_acq_rel)` |`amo<op>.{w|d}.aqrl` -|`atomic_<op>(memory_order_seq_cst) ` |`amo<op>.{w|d}.aqrl ` +|`atomic_<op>(memory_order_seq_cst)` |`amo<op>.{w|d}.aqrl` |C/C++ Construct |RVWMO LR/SC Mapping -|`atomic_<op>(memory_order_relaxed)` |`loop:lr.{w|d}; <op>; sc.{w|d}; ` +|`atomic_<op>(memory_order_relaxed)` |`loop:lr.{w|d}; <op>; sc.{w|d};` -| |`bnez loop ` +| |`bnez loop` |`atomic_<op>(memory_order_acquire)` -|`loop:lr.{w|d}.aq; <op>; sc.{w|d}; ` +|`loop:lr.{w|d}.aq; <op>; sc.{w|d};` -| |`bnez loop ` +| |`bnez loop` |`atomic_<op>(memory_order_release)` -|`loop:lr.{w|d}; <op>; sc.{w|d}.rl; ` +|`loop:lr.{w|d}; <op>; sc.{w|d}.rl;` -| |`bnez loop ` +| |`bnez loop` |`atomic_<op>(memory_order_acq_rel)` -|`loop:lr.{w|d}.aq; <op>; sc.{w|d}.rl; ` +|`loop:lr.{w|d}.aq; <op>; sc.{w|d}.rl;` -| |`bnez loop ` +| |`bnez loop` -|`atomic_<op>(memory_order_seq_cst)` |`loop:lr.{w|d}.aqrl; <op>; ` +|`atomic_<op>(memory_order_seq_cst)` |`loop:lr.{w|d}.aqrl; <op>;` -| |`sc.{w|d}.rl; bnez loop ` +| |`sc.{w|d}.rl; bnez loop` |=== [[tab:c11mappings_hypothetical]] @@ -1376,63 +1390,63 @@ native load-acquire and store-release opcodes are introduced. [cols="<,<",options="header",] |=== |C/C++ Construct |RVWMO Mapping -|Non-atomic load |`l{b|h|w|d} ` +|Non-atomic load |`l{b|h|w|d}` -|`atomic_load(memory_order_relaxed) ` |`l{b|h|w|d} ` +|`atomic_load(memory_order_relaxed)` |`l{b|h|w|d}` -|`atomic_load(memory_order_acquire) ` |`l{b|h|w|d}.aq ` +|`atomic_load(memory_order_acquire)` |`l{b|h|w|d}.aq` -|`atomic_load(memory_order_seq_cst) ` |`l{b|h|w|d}.aq ` +|`atomic_load(memory_order_seq_cst)` |`l{b|h|w|d}.aq` -|Non-atomic store |`s{b|h|w|d} ` +|Non-atomic store |`s{b|h|w|d}` -|`atomic_store(memory_order_relaxed) ` |`s{b|h|w|d} ` +|`atomic_store(memory_order_relaxed)` |`s{b|h|w|d}` -|`atomic_store(memory_order_release) ` |`s{b|h|w|d}.rl ` +|`atomic_store(memory_order_release)` |`s{b|h|w|d}.rl` -|`atomic_store(memory_order_seq_cst) ` |`s{b|h|w|d}.rl ` +|`atomic_store(memory_order_seq_cst)` |`s{b|h|w|d}.rl` -|`atomic_thread_fence(memory_order_acquire) ` |`fence r,rw ` +|`atomic_thread_fence(memory_order_acquire)` |`fence r,rw` -|`atomic_thread_fence(memory_order_release) ` |`fence rw,w ` +|`atomic_thread_fence(memory_order_release)` |`fence rw,w` -|`atomic_thread_fence(memory_order_acq_rel) ` |`fence.tso` +|`atomic_thread_fence(memory_order_acq_rel)` |`fence.tso` -|`atomic_thread_fence(memory_order_seq_cst) ` |`fence rw,rw ` +|`atomic_thread_fence(memory_order_seq_cst)` |`fence rw,rw` |C/C++ Construct |RVWMO AMO Mapping -|`atomic_<op>(memory_order_relaxed) ` |`amo<op>.{w|d} ` +|`atomic_<op>(memory_order_relaxed)` |`amo<op>.{w|d}` -|`atomic_<op>(memory_order_acquire) ` |`amo<op>.{w|d}.aq ` +|`atomic_<op>(memory_order_acquire)` |`amo<op>.{w|d}.aq` -|`atomic_<op>(memory_order_release) ` |`amo<op>.{w|d}.rl ` +|`atomic_<op>(memory_order_release)` |`amo<op>.{w|d}.rl` -|`atomic_<op>(memory_order_acq_rel) ` |`amo<op>.{w|d}.aqrl ` +|`atomic_<op>(memory_order_acq_rel)` |`amo<op>.{w|d}.aqrl` -|`atomic_<op>(memory_order_seq_cst) ` |`amo<op>.{w|d}.aqrl ` +|`atomic_<op>(memory_order_seq_cst)` |`amo<op>.{w|d}.aqrl` |C/C++ Construct |RVWMO LR/SC Mapping -|`atomic_<op>(memory_order_relaxed) ` |`lr.{w|d}; <op>; sc.{w|d} ` +|`atomic_<op>(memory_order_relaxed)` |`lr.{w|d}; <op>; sc.{w|d}` -|`atomic_<op>(memory_order_acquire) ` |`lr.{w|d}.aq; <op>; sc.{w|d} ` +|`atomic_<op>(memory_order_acquire)` |`lr.{w|d}.aq; <op>; sc.{w|d}` -|`atomic_<op>(memory_order_release) ` |`lr.{w|d}; <op>; sc.{w|d}.rl ` +|`atomic_<op>(memory_order_release)` |`lr.{w|d}; <op>; sc.{w|d}.rl` -|`atomic_<op>(memory_order_acq_rel) ` |`lr.{w|d}.aq; <op>; sc.{w|d}.rl ` +|`atomic_<op>(memory_order_acq_rel)` |`lr.{w|d}.aq; <op>; sc.{w|d}.rl` -|`atomic_<op>(memory_order_seq_cst) ` -|`lr.{w|d}.aq^*; <op>; sc.{w|d}.rl ` +|`atomic_<op>(memory_order_seq_cst)` +|`lr.{w|d}.aq^*; <op>; sc.{w|d}.rl` |latexmath:[$^*$]must be `lr.{w|d}.aqrl` in order to interoperate with -code mapped per Table #tab:c11mappings[1.6] | +code mapped per Table #tab:c11mappings[1.6] | |=== -Table #tab:c11mappings[1.6] provides a mapping of C11/C++11 atomic +Table #tab:c11mappings[1.6] provides a mapping of C11/C++11 atomic operations onto RISC-V memory instructions. If load and store opcodes with _aq_ and _rl_ modifiers are introduced, then the mappings in -Table #tab:c11mappings_hypothetical[1.7] will suffice. Note however that +Table #tab:c11mappings_hypothetical[1.7] will suffice. Note however that the two mappings only interoperate correctly if `atomic_<op>(memory_order_seq_cst)` is mapped using an LR that has both _aq_ and _rl_ set. @@ -1443,10 +1457,10 @@ to originate from the SC, and that any PPO orderings that terminate at the SC are also made to terminate at the LR. For example, the LR must also be made to respect any data dependencies that the AMO has, given that load operations do not otherwise have any notion of a data -dependency. Likewise, the effect a FENCE R,R elsewhere in the same hart +dependency. Likewise, the effect a FENCE R,R elsewhere in the same hart must also be made to apply to the SC, which would not otherwise respect that fence. The emulator may achieve this effect by simply mapping AMOs -onto `lr.aq; <op>; sc.aqrl`, matching the mapping used elsewhere for +onto `lr.aq; <op>; sc.aqrl`, matching the mapping used elsewhere for fully ordered atomics. These C11/C++11 mappings require the platform to provide the following @@ -1478,7 +1492,7 @@ guidelines on how architects and programmers should interpret the models’ rules. Both RVWMO and RVTSO are multi-copy atomic (or -``other-multi-copy-atomic``): any store value that is visible to a hart +`other-multi-copy-atomic`): any store value that is visible to a hart other than the one that originally issued it must also be conceptually visible to all other harts in the system. In other words, harts may forward from their own previous stores before those stores have become @@ -1513,10 +1527,10 @@ of important data structures. #ppo:rdw[[ppo:rdw]]–#ppo:amoforward[[ppo:amoforward]] and #ppo:addrdatarfi[[ppo:addrdatarfi]]–#ppo:addrpo[[ppo:addrpo]] directly. These are included to facilitate common microarchitectural optimizations -(rule #ppo:rdw[[ppo:rdw]]) and the operational formal modeling approach +(rule #ppo:rdw[[ppo:rdw]]) and the operational formal modeling approach (rules #ppo:amoforward[[ppo:amoforward]] and #ppo:addrdatarfi[[ppo:addrdatarfi]]–#ppo:addrpo[[ppo:addrpo]]) described -in Section #sec:operational[[sec:operational]]. They also facilitate the +in Section #sec:operational[[sec:operational]]. They also facilitate the process of porting code from other architectures that have similar rules. @@ -1535,20 +1549,20 @@ architects, but it is a standard memory model requirement hardware implementations will enforce naturally, unless they contain extreme optimizations. Of course, implementations should make sure to double check these rules nevertheless. Hardware must also ensure that -syntactic dependencies are not ``optimized away``. +syntactic dependencies are not `optimized away`. Architectures are free to implement any of the memory model rules as conservatively as they choose. For example, a hardware implementation may choose to do any or all of the following: -* interpret all fences as if they were FENCE RW,RW (or FENCE IORW,IORW, +* interpret all fences as if they were FENCE RW,RW (or FENCE IORW,IORW, if I/O is involved), regardless of the bits actually set -* implement all fences with PW and SR as if they were FENCE RW,RW (or -FENCE IORW,IORW, if I/O is involved), as PW with SR is the most +* implement all fences with PW and SR as if they were FENCE RW,RW (or +FENCE IORW,IORW, if I/O is involved), as PW with SR is the most expensive of the four possible main memory ordering components anyway -* emulate _aq_ and _rl_ as described in Section #sec:memory:porting[1.5] +* emulate _aq_ and _rl_ as described in Section #sec:memory:porting[1.5] * enforcing all same-address load-load ordering, even in the presence of -patterns such as ``fri-rfi`` and ``RSW`` +patterns such as `fri-rfi` and `RSW` * forbid any forwarding of a value from a store in the store buffer to a subsequent AMO or LR to the same address * forbid any forwarding of a value from an AMO or SC in the store buffer @@ -1576,7 +1590,7 @@ value in memory (e.g., an AMOMAX for which the value in _rs2_ is smaller than the value currently in memory) are still semantically considered store operations. Microarchitectures that attempt to implement silent stores must take care to ensure that the memory model is still obeyed, -particularly in cases such as RSW (Section #sec:memory:overlap[1.3.5]) +particularly in cases such as RSW (Section #sec:memory:overlap[1.3.5]) which tend to be incompatible with silent stores. * Writes may be merged (i.e., two consecutive writes to the same address may be merged) or subsumed (i.e., the earlier of two back-to-back writes @@ -1600,7 +1614,7 @@ m.4m.1m.4 ` ` & & -As written, if the load (d) reads value latexmath:[$1$], then (a) must +As written, if the load (d) reads value latexmath:[$1$], then (a) must precede (f) in the global memory order: * {empty}(a) precedes (c) in the global memory order because of rule 2 @@ -1610,8 +1624,8 @@ Value axiom * {empty}(e) precedes (f) in the global memory order because of rule 1 In other words the final value of the memory location whose address is -in `s0` must be latexmath:[$2$] (the value written by the store (f)) and -cannot be latexmath:[$3$] (the value written by the store (a)). +in `s0` must be latexmath:[$2$] (the value written by the store (f)) and +cannot be latexmath:[$3$] (the value written by the store (a)). A very aggressive microarchitecture might erroneously decide to discard (e), as (f) supersedes it, and this may in turn lead the @@ -1685,7 +1699,7 @@ would be compatible with the RVWMO memory model: There is a known discrepancy between the operational and axiomatic specifications within the family of mixed-size RSW variants shown in -Figures #fig:litmus:discrepancy:rsw1[[fig:litmus:discrepancy:rsw1]]–#fig:litmus:discrepancy:rsw3[[fig:litmus:discrepancy:rsw3]]. +Figures #fig:litmus:discrepancy:rsw1[[fig:litmus:discrepancy:rsw1]]–#fig:litmus:discrepancy:rsw3[[fig:litmus:discrepancy:rsw3]]. To address this, we may choose to add something like the following new PPO rule: Memory operation latexmath:[$a$] precedes memory operation latexmath:[$b$] in preserved program order (and hence also in the global diff --git a/src/q-st-ext.adoc b/src/q-st-ext.adoc index 02122b7..bd2da55 100644 --- a/src/q-st-ext.adoc +++ b/src/q-st-ext.adoc @@ -17,17 +17,10 @@ value. New 128-bit variants of LOAD-FP and STORE-FP instructions are added, encoded with a new value for the funct3 width field. -M@R@F@R@O + -& & & & + -& & & & + -& 5 & 3 & 5 & 7 + -offset[11:0] & base & Q & dest & LOAD-FP + - -O@R@R@F@R@O + -& & & & & + -& & & & & + -& 5 & 5 & 3 & 5 & 7 + -offset[11:5] & src & base & Q & offset[4:0] & STORE-FP + +include::images/wavedrom/quad-ls.adoc[] +[[quad-ls]] +.Quad-precision load and store +image::image_placeholder.png[] FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128. @@ -55,20 +48,10 @@ The quad-precision floating-point computational instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands and produce quad-precision results. -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FADD/FSUB & Q & src2 & src1 & RM & dest & OP-FP + -FMUL/FDIV & Q & src2 & src1 & RM & dest & OP-FP + -FMIN-MAX & Q & src2 & src1 & MIN/MAX & dest & OP-FP + -FSQRT & Q & 0 & src & RM & dest & OP-FP + - -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -src3 & Q & src2 & src1 & RM & dest & F[N]MADD/F[N]MSUB + +include::images/wavedrom/quad-compute.adoc[] +[[quad-compute]] +.Quad-precision computational +image::image_placeholder.png[] === Quad-Precision Convert and Move Instructions @@ -83,12 +66,10 @@ FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only instructions. -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FCVT._int_.Q & Q & W[U]/L[U] & src & RM & dest & OP-FP + -FCVT.Q._int_ & Q & W[U]/L[U] & src & RM & dest & OP-FP + +include::images/wavedrom/quad-cnvrt-mv.adoc[] +[[quad-cnvrt-mv]] +.Quad-precision convert and move +image::image_placeholder.png[] New floating-point-to-floating-point conversion instructions are added. These instructions are defined analogously to the double-precision @@ -98,42 +79,39 @@ single-precision floating-point number, or vice-versa, respectively. FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to a double-precision floating-point number, or vice-versa, respectively. -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FCVT.S.Q & S & Q & src & RM & dest & OP-FP + -FCVT.Q.S & Q & S & src & RM & dest & OP-FP + -FCVT.D.Q & D & Q & src & RM & dest & OP-FP + -FCVT.Q.D & Q & D & src & RM & dest & OP-FP + +include::images/wavedrom/quad-cnvt-interchange.adoc[] +[[quad-convrt-interchange]] +.Quad-precision convert and move interchangeably +image::image_placeholder.png[] Floating-point to floating-point sign-injection instructions, FSGNJ.Q, FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision sign-injection instruction. -R@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FSGNJ & Q & src2 & src1 & J[N]/JX & dest & OP-FP + +include::images/wavedrom/quad-cnvrt-intch-xqqx.adoc[] +[[quad-cnvrt-intch-xqqx]] +.Quad-precision convert and move interchangeably XQ-QX +image::image_placeholder.png[] FMV.X.Q and FMV.Q.X instructions are not provided in RV32 or RV64, so quad-precision bit patterns must be moved to the integer registers via memory. +[NOTE] +==== RV128 will support FMV.X.Q and FMV.Q.X in the Q extension. +==== -=== Quad-Precision Floating-Point Compare Instructions +=== Quad-precision floating-Point compare The quad-precision floating-point compare instructions are defined analogously to their double-precision counterparts, but operate on quad-precision operands. -S@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FCMP & Q & src2 & src1 & EQ/LT/LE & dest & OP-FP + +include::images/wavedrom/quad-float-compare.adoc[] +[[quad-float-compare]] +.Quad-precision floatinf-point compare +image::image_placeholder.png[] === Quad-Precision Floating-Point Classify Instruction @@ -141,8 +119,17 @@ The quad-precision floating-point classify instruction, FCLASS.Q, is defined analogously to its double-precision counterpart, but operates on quad-precision operands. -S@F@R@R@F@R@O + -& & & & & & + -& & & & & & + -& 2 & 5 & 5 & 3 & 5 & 7 + -FCLASS & Q & 0 & src & 001 & dest & OP-FP + +include::images/wavedrom/quad-float-clssfy.adoc[] +[[quad-float-clssfy]] +.Quad-precision floating point classify +image::image_placeholder.png[] + + +dart taser + +debra stuart +lady +541-267-5915 + + + diff --git a/src/riscv-isa-unpriv-conv-review.adoc b/src/riscv-isa-unpr-conv-review.adoc index 2f3c349..2f3c349 100644 --- a/src/riscv-isa-unpriv-conv-review.adoc +++ b/src/riscv-isa-unpr-conv-review.adoc diff --git a/src/riscv-isa-unpr-conv-review.pdf b/src/riscv-isa-unpr-conv-review.pdf Binary files differindex abb169a..3b727b5 100644 --- a/src/riscv-isa-unpr-conv-review.pdf +++ b/src/riscv-isa-unpr-conv-review.pdf |
