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| author | Andrew Waterman <andrew@sifive.com> | 2021-01-13 15:15:33 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-01-13 15:15:33 -0800 |
| commit | 9c8b8f36b31c3cefdb6b57f5073b374c17196def (patch) | |
| tree | 732a65d21798f0d1db47658d913082120fda1f23 /src | |
| parent | 02e8477fb3570329f96c266463533b9c995d2fdd (diff) | |
| download | riscv-isa-manual-9c8b8f36b31c3cefdb6b57f5073b374c17196def.zip riscv-isa-manual-9c8b8f36b31c3cefdb6b57f5073b374c17196def.tar.gz riscv-isa-manual-9c8b8f36b31c3cefdb6b57f5073b374c17196def.tar.bz2 | |
Add preface note that N extension was moved to its own chapter
Diffstat (limited to 'src')
| -rw-r--r-- | src/priv-preface.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 69627ab..f8b0642 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -51,6 +51,7 @@ Additionally, the following compatible changes have been made since version \begin{itemize} \parskip 0pt \itemsep 1pt +\item Moved N extension into its own chapter. \item Defined the RV32-only CSR {\tt mstatush}, which contains most of the same fields as the upper 32 bits of RV64's {\tt mstatus}. \item Permitted the unconditional delegation of less-privileged interrupts. |