table fixes

6 files changed, 175 insertions, 219 deletions

diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc
index f750a33..7ea67ac 100644
--- a/src/c-st-ext.adoc
+++ b/src/c-st-ext.adoc
@@ -226,44 +226,43 @@ For many RVC instructions, zero-valued immediates are disallowed and
 _x0_ is not a valid 5-bit register specifier. These restrictions free up
 encoding space for other instructions requiring fewer operand bits.
 
-//include::images/wavedrom/cr-register.adoc[]
-//[cr-register]
-//.Compressed 16-bit RVC instruction formats
-//image::image_placeholder.png[]
-//(((compressed, 16-bit)))
+[[cr-register]]
+include::images/wavedrom/cr-register.adoc[]
+.Compressed 16-bit RVC instructions
+image::image_placeholder.png[]
+(((compressed, 16-bit)))
 
 [[rvc-form]]
 .Compressed 16-bit RVC instruction formats.
-//[cols="^,^,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<",]
+[%header,cols="^,^,<,<,<,<,<,"]
 |===
 
-|Format |Meaning | | | | | | | | | | | | |
+|Format |Meaning 2+|15 14 13 12 |11 10 9 8 7 2+|6 5 4 3 2 | 1 0
 
-|CR |Register |funct4| |rd/rs1 | | |rs2 | | | | |op | |
+|CR |Register 2+|funct4| rd/rs1 2+|rs2 |  op
 
-|CI |Immediate |funct3 |imm |rd/rs1 | | |imm | | | | |op | |
+|CI |Immediate |funct3 |imm |rd/rs1  2+|imm |  op
 
-|CSS |Stack-relative Store |funct3|imm | | | |rs2 | | | | |op |
-|
+|CSS |Stack-relative Store |funct3 2+|imm  2+|rs2 |  op
 
-|CIW |Wide Immediate |funct3|imm | | | | | |rdlatexmath:[$'$]| | |op | |
+|CIW |Wide Immediate |funct3 3+|imm |rd l'| op
 
-|CL |Load |funct3 |imm |rs1 latexmath:[$'$] | | |imm | |rd latexmath:[$'$] | | |op | |
+|CL |Load |funct3 |imm |rs1 l' | imm |rd ' | op
 
-|CS |Store |funct3 |imm |rs1 latexmath:[$'$] | | |imm | |rs2 latexmath:[$'$] | | |op | |
+|CS |Store |funct3 |imm |rs1 l' | imm |rs2 ' | op
 
-|CA |Arithmetic |funct6 | |rd latexmath:[$'$]/rs1 latexmath:[$'$] | | |funct2 | |rs2 latexmath:[$'$] | | |op | |
+|CA |Arithmetic 2+|funct6|rd l'/rs1 l' |funct2 |rs2 l' | op
 
-|CB |Branch/Arithmetic |funct3 |offset |rd latexmath:[$'$]/rs1 latexmath:[$'$] | | |offset | | | | |op | |
+|CB |Branch/Arithmetic |funct3 |offset |rd l'/rs1 l'  2+|offset | op
 
-|CJ |Jump |funct3 |jump target | | | | | | | | |op | |
+|CJ |Jump |funct3 4+|jump target  | op
 |===
 
 [registers]
-.Registers specified by the three-bit _rs1 latexmath:[$'$]_,
-_rs2 latexmath:[$'$]_, and _rd latexmath:[$'$]_ fields of the CIW, CL,
+.Registers specified by the three-bit _rs1 l'_,
+_rs2 l'_, and _rd l'_ fields of the CIW, CL,
 CS, CA, and CB formats.
-[cols="<,^,^,^,^,^,^,^,^",]
+[%header,cols="20%,10%,10%,10%,10%,10%,10%,10%,10%"]
 |===
 |RVC Register Number |000 |001 |010 |011 |100 |101 |110 |111
 
@@ -406,47 +405,42 @@ attain the greatest code size reduction.
 
 ==== Register-Based Loads and Stores
 
-S@S@S@Y@S@Y +
-& & & & & +
-& & & & & +
-& 3 & 3 & 2 & 3 & 2 +
-C.LW & offset[5:3] & base & offset[2latexmath:[$\vert$]6] & dest & C0 +
-C.LD & offset[5:3] & base & offset[7:6] & dest & C0 +
-C.LQ & offset[5latexmath:[$\vert$]4latexmath:[$\vert$]8] & base &
-offset[7:6] & dest & C0 +
-C.FLW& offset[5:3] & base & offset[2latexmath:[$\vert$]6] & dest & C0 +
-C.FLD& offset[5:3] & base & offset[7:6] & dest & C0 +
+[[reg-based-ldnstr]]
+include::images/wavedrom/reg-based-ldnstr.adoc[]
+.Compressed, register-Based Loads and Stores
+image::image_placeholder.png[]
+(((compressed, regoster-based load and store)))
 
 These instructions use the CL format.
 
 C.LW loads a 32-bit value from memory into register
-_rd latexmath:[$'$]_. It computes an effective address by adding the
+_rd l'_. It computes an effective address by adding the
 _zero_-extended offset, scaled by 4, to the base address in register
-_rs1 latexmath:[$'$]_. It expands to _lw rd, offset(rs1)_.
+_rs1 l'_. It expands to _lw rd, offset(rs1)_.
 
 C.LD is an RV64C/RV128C-only instruction that loads a 64-bit value from
-memory into register _rd latexmath:[$'$]_. It computes an effective
+memory into register _rd l'_. It computes an effective
 address by adding the _zero_-extended offset, scaled by 8, to the base
-address in register _rs1 latexmath:[$'$]_. It expands to
+address in register _rs1 l'_. It expands to
 _ld rd', offset(rs1')_.
 
 C.LQ is an RV128C-only instruction that loads a 128-bit value from
-memory into register _rd latexmath:[$'$]_. It computes an effective
+memory into register _rd l'_. It computes an effective
 address by adding the _zero_-extended offset, scaled by 16, to the base
-address in register _rs1 latexmath:[$'$]_. It expands to
+address in register _rs1 l'_. It expands to
 _lq rd, offset(rs1)_.
 
 C.FLW is an RV32FC-only instruction that loads a single-precision
 floating-point value from memory into floating-point register
-_rd latexmath:[$'$]_. It computes an effective address by adding the
+_rd l'_. It computes an effective address by adding the
 _zero_-extended offset, scaled by 4, to the base address in register
-_rs1 latexmath:[$'$]_. It expands to _flw rd, offset(rs1)_.
+_rs1 l'_. It expands to _flw rd, offset(rs1)_.
 
 C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision
 floating-point value from memory into floating-point register
-_rd latexmath:[$'$]_. It computes an effective address by adding the
+_rd l'_. It computes an effective address by adding the
 _zero_-extended offset, scaled by 8, to the base address in register
-_rs1 latexmath:[$'$]_. It expands to _fld rd, offset(rs1)_.
+_rs1 l'_. It expands to _fld rd, offset(rs1)_.
 
 S@S@S@Y@S@Y +
 & & & & & +
@@ -461,34 +455,34 @@ C.FSD& offset[5:3] & base & offset[7:6] & src & C0 +
 
 These instructions use the CS format.
 
-C.SW stores a 32-bit value in register _rs2 latexmath:[$'$]_ to memory.
+C.SW stores a 32-bit value in register _rs2 l'_ to memory.
 It computes an effective address by adding the _zero_-extended offset,
-scaled by 4, to the base address in register _rs1 latexmath:[$'$]_. It
+scaled by 4, to the base address in register _rs1 l'_. It
 expands to _sw rs2, offset(rs1)_.
 
 C.SD is an RV64C/RV128C-only instruction that stores a 64-bit value in
-register _rs2 latexmath:[$'$]_ to memory. It computes an effective
+register _rs2 l'_ to memory. It computes an effective
 address by adding the _zero_-extended offset, scaled by 8, to the base
-address in register _rs1 latexmath:[$'$]_. It expands to
+address in register _rs1 l'_. It expands to
 _sd rs2, offset(rs1)_.
 
 C.SQ is an RV128C-only instruction that stores a 128-bit value in
-register _rs2 latexmath:[$'$]_ to memory. It computes an effective
+register _rs2 l'_ to memory. It computes an effective
 address by adding the _zero_-extended offset, scaled by 16, to the base
-address in register _rs1 latexmath:[$'$]_. It expands to
+address in register _rs1 l'_. It expands to
 _sq rs2, offset(rs1)_.
 
 C.FSW is an RV32FC-only instruction that stores a single-precision
-floating-point value in floating-point register _rs2 latexmath:[$'$]_ to
+floating-point value in floating-point register _rs2 l'_ to
 memory. It computes an effective address by adding the _zero_-extended
 offset, scaled by 4, to the base address in register
-_rs1 latexmath:[$'$]_. It expands to _fsw rs2, offset(rs1)_.
+_rs1 l'_. It expands to _fsw rs2, offset(rs1)_.
 
 C.FSD is an RV32DC/RV64DC-only instruction that stores a
 double-precision floating-point value in floating-point register
-_rs2 latexmath:[$'$]_ to memory. It computes an effective address by
+_rs2 l'_ to memory. It computes an effective address by
 adding the _zero_-extended offset, scaled by 8, to the base address in
-register _rs1 latexmath:[$'$]_. It expands to
+register _rs1 l'_. It expands to
 _fsd rs2, offset(rs1)_.
 
 === Control Transfer Instructions
@@ -524,8 +518,8 @@ E@T@T@Y +
 & & & +
 & & & +
 & 5 & 5 & 2 +
-C.JR & srclatexmath:[$\neq$]0 & 0 & C2 +
-C.JALR & srclatexmath:[$\neq$]0 & 0 & C2 +
+C.JR & src&#8800;0 & 0 & C2 +
+C.JALR & src&#8800;0 & 0 & C2 +
 
 These instructions use the CR format.
 
@@ -564,11 +558,11 @@ These instructions use the CB format.
 C.BEQZ performs conditional control transfers. The offset is
 sign-extended and added to the _pc_ to form the branch target address.
 It can therefore target a latexmath:[$\pm$] range. C.BEQZ takes the
-branch if the value in register _rs1 latexmath:[$'$]_ is zero. It
+branch if the value in register _rs1 l'_ is zero. It
 expands to _beq rs1, x0, offset_.
 
 C.BNEZ is defined analogously, but it takes the branch if
-_rs1 latexmath:[$'$]_ contains a nonzero value. It expands to
+_rs1 l'_ contains a nonzero value. It expands to
 _bne rs1, x0, offset_.
 
 === Integer Computational Instructions
@@ -585,19 +579,19 @@ S@W@T@T@Y +
 & & & & +
 & & & & +
 & 1 & 5 & 5 & 2 +
-C.LI & imm[5] & destlatexmath:[$\neq$]0 & imm[4:0] & C1 +
+C.LI & imm[5] & dest&#8800;0 & imm[4:0] & C1 +
 C.LUI & nzimm[17] &
 latexmath:[$\textrm{dest}{\neq}{\left\{0,2\right\}}$] & nzimm[16:12] &
 C1 +
 
 C.LI loads the sign-extended 6-bit immediate, _imm_, into register _rd_.
 C.LI expands into _addi rd, x0, imm_. C.LI is only valid when
-_rd_latexmath:[$\neq$]_x0_; the code points with _rd_=_x0_ encode HINTs.
+_rd_&#8800;_x0_; the code points with _rd_=_x0_ encode HINTs.
 
 C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the
 destination register, clears the bottom 12 bits, and sign-extends bit 17
 into all higher bits of the destination. C.LUI expands into
-_lui rd, nzimm_. C.LUI is only valid when
+_lui rd, nzimm_. C.LUI is only valid when _rd_
 latexmath:[$\textit{rd}{\neq}{\left\{\texttt{x0},\texttt{x2}\right\}}$],
 and when the immediate is not equal to zero. The code points with
 _nzimm_=0 are reserved; the remaining code points with _rd_=_x0_ are
@@ -613,8 +607,8 @@ S@W@T@T@Y +
 & & & & +
 & & & & +
 & 1 & 5 & 5 & 2 +
-C.ADDI & nzimm[5] & destlatexmath:[$\neq$]0 & nzimm[4:0] & C1 +
-C.ADDIW & imm[5] & destlatexmath:[$\neq$]0 & imm[4:0] & C1 +
+C.ADDI & nzimm[5] & dest&#8800;0 & nzimm[4:0] & C1 +
+C.ADDIW & imm[5] & dest&#8800;0 & imm[4:0] & C1 +
 C.ADDI16SP & nzimm[9] & 2 &
 nzimm[4latexmath:[$\vert$]6latexmath:[$\vert$]8:7latexmath:[$\vert$]5] &
 C1 +
@@ -622,7 +616,7 @@ C1 +
 C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in
 register _rd_ then writes the result to _rd_. C.ADDI expands into
 _addi rd, rd, nzimm_. C.ADDI is only valid when
-_rd_latexmath:[$\neq$]_x0_ and _nzimm_latexmath:[$\neq$]0. The code
+_rd_&#8800;_x0_ and _nzimm_&#8800;0. The code
 points with _rd_=_x0_ encode the C.NOP instruction; the remaining code
 points with _nzimm_=0 encode HINTs.
 
@@ -630,7 +624,7 @@ C.ADDIW is an RV64C/RV128C-only instruction that performs the same
 computation but produces a 32-bit result, then sign-extends result to 64
 bits. C.ADDIW expands into _addiw rd, rd, imm_. The immediate can be
 zero for C.ADDIW, where this corresponds to _sext.w rd_. C.ADDIW is
-only valid when _rd_latexmath:[$\neq$]_x0_; the code points with
+only valid when _rd_&#8800;_x0_; the code points with
 _rd_=_x0_ are reserved.
 
 C.ADDI16SP shares the opcode with C.LUI, but has a destination field of
@@ -639,7 +633,7 @@ value in the stack pointer (_sp_=_x2_), where the immediate is scaled to
 represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to
 adjust the stack pointer in procedure prologues and epilogues. It
 expands into _addi x2, x2, nzimm_. C.ADDI16SP is only valid when
-_nzimm_latexmath:[$\neq$]0; the code point with _nzimm_=0 is reserved.
+_nzimm_&#8800;0; the code point with _nzimm_=0 is reserved.
 
 [NOTE]
 ====
@@ -659,14 +653,14 @@ C.ADDI4SPN is a CIW-format instruction that adds a _zero_-extended
 non-zero immediate, scaled by 4, to the stack pointer, _x2_, and writes
 the result to _rd_. This instruction is used to generate pointers to
 stack-allocated variables, and expands to _addi rd, x2, nzuimm_.
-C.ADDI4SPN is only valid when _nzuimm_latexmath:[$\neq$]0; the code
+C.ADDI4SPN is only valid when _nzuimm_&#8800;0; the code
 points with _nzuimm_=0 are reserved.
 
 S@W@T@T@Y +
 & & & & +
 & & & & +
 & 1 & 5 & 5 & 2 +
-C.SLLI & shamt[5] & destlatexmath:[$\neq$]0 & shamt[4:0] & C2 +
+C.SLLI & shamt[5] & dest&#8800;0 & shamt[4:0] & C2 +
 
 C.SLLI is a CI-format instruction that performs a logical left shift of
 the value in register _rd_ then writes the result to _rd_. The shift
@@ -689,8 +683,8 @@ C.SRLI & shamt[5] & C.SRLI & dest & shamt[4:0] & C1 +
 C.SRAI & shamt[5] & C.SRAI & dest & shamt[4:0] & C1 +
 
 C.SRLI is a CB-format instruction that performs a logical right shift of
-the value in register _rd latexmath:[$'$]_ then writes the result to
-_rd latexmath:[$'$]_. The shift amount is encoded in the _shamt_ field.
+the value in register _rd l'_ then writes the result to
+_rd l'_. The shift amount is encoded in the _shamt_ field.
 For RV128C, a shift amount of zero is used to encode a shift of 64.
 Furthermore, the shift amount is sign-extended for RV128C, and so the
 legal shift amounts are 1–31, 64, and 96–127. C.SRLI expands into
@@ -725,8 +719,8 @@ S@W@Y@S@T@Y +
 C.ANDI & imm[5] & C.ANDI & dest & imm[4:0] & C1 +
 
 C.ANDI is a CB-format instruction that computes the bitwise AND of the
-value in register _rd latexmath:[$'$]_ and the sign-extended 6-bit
-immediate, then writes the result to _rd latexmath:[$'$]_. C.ANDI
+value in register _rd l'_ and the sign-extended 6-bit
+immediate, then writes the result to _rd l'_. C.ANDI
 expands to _andi rd, rd, imm_.
 
 ==== Integer Register-Register Operations
@@ -735,8 +729,8 @@ E@T@T@Y +
 & & & +
 & & & +
 & 5 & 5 & 2 +
-C.MV & destlatexmath:[$\neq$]0 & srclatexmath:[$\neq$]0 & C2 +
-C.ADD & destlatexmath:[$\neq$]0 & srclatexmath:[$\neq$]0 & C2 +
+C.MV & dest&#8800;0 & src&#8800;0 & C2 +
+C.ADD & dest&#8800;0 & src&#8800;0 & C2 +
 
 These instructions use the CR format.
 
@@ -779,35 +773,35 @@ C.SUBW & dest & C.SUBW & src & C1 +
 These instructions use the CA format.
 
 C.AND computes the bitwise AND of the values in registers
-_rd latexmath:[$'$]_ and _rs2 latexmath:[$'$]_, then writes the result
-to register _rd latexmath:[$'$]_. C.AND expands into
+_rd l'_ and _rs2 l'_, then writes the result
+to register _rd l'_. C.AND expands into
 _and rd, rd, rs2_.
 
 C.OR computes the bitwise OR of the values in registers
-_rd latexmath:[$'$]_ and _rs2 latexmath:[$'$]_, then writes the result
-to register _rd latexmath:[$'$]_. C.OR expands into
+_rd l'_ and _rs2 l'_, then writes the result
+to register _rd l'_. C.OR expands into
 _or rd&#8242;, rd&#8242;, rs2&#8242;_.
 
 C.XOR computes the bitwise XOR of the values in registers
-_rd latexmath:[$'$]_ and _rs2 latexmath:[$'$]_, then writes the result
-to register _rd latexmath:[$'$]_. C.XOR expands into
+_rd l'_ and _rs2 l'_, then writes the result
+to register _rd l'_. C.XOR expands into
 _xor rd', rd', rs2'_.
 
-C.SUB subtracts the value in register _rs2 latexmath:[$'$]_ from the
-value in register _rd latexmath:[$'$]_, then writes the result to
-register _rd latexmath:[$'$]_. C.SUB expands into
+C.SUB subtracts the value in register _rs2 l'_ from the
+value in register _rd l'_, then writes the result to
+register _rd l'_. C.SUB expands into
 _sub rd', rd', rs2'_.
 
 C.ADDW is an RV64C/RV128C-only instruction that adds the values in
-registers _rd latexmath:[$'$]_ and _rs2 latexmath:[$'$]_, then
+registers _rd l'_ and _rs2 l'_, then
 sign-extends the lower 32 bits of the sum before writing the result to
-register _rd latexmath:[$'$]_. C.ADDW expands into
+register _rd l'_. C.ADDW expands into
 _addw rd', rd', rs2'_.
 
 C.SUBW is an RV64C/RV128C-only instruction that subtracts the value in
-register _rs2 latexmath:[$'$]_ from the value in register
-_rd latexmath:[$'$]_, then sign-extends the lower 32 bits of the
-difference before writing the result to register _rd latexmath:[$'$]_.
+register _rs2 l'_ from the value in register
+_rd l'_, then sign-extends the lower 32 bits of the
+difference before writing the result to register _rd l'_.
 C.SUBW expands into _subw rd', rd', rs2'_.
 
 [NOTE]
@@ -851,7 +845,7 @@ C.NOP & 0 & 0 & 0 & C1 +
 C.NOP is a CI-format instruction that does not change any user-visible
 state, except for advancing the _pc_ and incrementing any applicable
 performance counters. C.NOP expands to _nop_. C.NOP is only valid when
-_imm_=0; the code points with _imm_latexmath:[$\neq$]0 encode HINTs.
+_imm_=0; the code points with _imm_&#8800;0 encode HINTs.
 
 ==== Breakpoint Instruction
 
@@ -924,28 +918,26 @@ no standard HINTs will ever be defined in this subspace.
 
 [[rvc-t-hints]]
 .RVC HINT instructions.
-//[cols="<,<,>,<",options="header",]
+[cols="<,<,>,<",options="header",]
 |===
 |Instruction |Constraints |Code Points |Purpose
-|C.NOP |_nzimm_latexmath:[$\neq$]0 |63 .6+^.>s|_Reserved for future standard
-use_
+|C.NOP |_nzimm_&#8800;0 |63 .6+^.>s|_Reserved for future standard use_
 
-|C.ADDI | _rd_latexmath:[$\neq$]_x0_, _nzimm_=0 |31
+|C.ADDI | _rd_&#8800;_x0_, _nzimm_=0 |31
 
 |C.LI | _rd_=_x0_ |64
 
-|C.LUI | _rd_=_x0_, _nzimm_latexmath:[$\neq$]0 |63
+|C.LUI | _rd_=_x0_, _nzimm_&#8800;0 |63
 
-|C.MV | _rd_=_x0_, _rs2_latexmath:[$\neq$]_x0_ |31
+|C.MV | _rd_=_x0_, _rs2_&#8800;_x0_ |31
 
-|C.ADD | _rd_=_x0_, _rs2_latexmath:[$\neq$]_x0_ |31
+|C.ADD | _rd_=_x0_, _rs2_&#8800;_x0_ |31
 
-|C.SLLI |_rd_=_x0_, _nzimm_latexmath:[$\neq$]0 |31 (RV32), 63 (RV64/128)  .5+^.>s|_Designated
-for custom use_
+|C.SLLI |_rd_=_x0_, _nzimm_&#8800;0 |31 (RV32), 63 (RV64/128)  .5+^.>s|_Designated for custom use_
 
 |C.SLLI64 | _rd_=_x0_ |1
 
-|C.SLLI64 | _rd_latexmath:[$\neq$]_x0_, RV32 and RV64 only |31
+|C.SLLI64 | _rd_&#8800;_x0_, RV32 and RV64 only |31
 
 |C.SRLI64 | RV32 and RV64 only |8
 
@@ -985,184 +977,134 @@ microarchitectural hints <<rvc-hints>>.
 
 [[rvc-instr-table0]]
 .Instruction listing for RVC, Quadrant 0
-//[cols="<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<",]
-|===
+[%header,format+DSV,separator=!,cols="10%,12%,12%,12%,6%,5%,41%"]
+!===
 
-|000|0 |  | | | | | |0 | | |00 |_Illegal instruction_
+!15 14 13 3+! 12  11 10 9 8 7  6 5 !4 3 2 ! 1 0 !
 
-|000|nzuimm[5:4 latexmath:[$\vert$]9:6latexmath:[$\vert$]2 latexmath:[$\vert$]3]
-| |  | | | | |rd latexmath:[$'$] | | |00 |C.ADDI4SPN _(RES,
-nzuimm=0)_
+!000 3+!0 ! 0 !00 !_Illegal instruction_
 
-|001|uimm[5:3] | |rs1 latexmath:[$'$] | | |uimm[7:6] |
-|rd latexmath:[$'$] | |00 |C.FLD _(RV32/64)_
+!000 3+!nzuimm[5:4|9:6|2|3] ! rd' !00 !C.ADDI4SPN _(RES,nzuimm=0)_
 
-|001|uimm[5:4latexmath:[$\vert$]8] | |rs1 latexmath:[$'$] | |
-|uimm[7:6] | |rd latexmath:[$'$] | | |00 |C.LQ _(RV128)_
+!001!uimm[5:3] !rs1 l' !uimm[7:6] !rd' !00 !C.FLD _(RV32/64)_
 
-|010|uimm[5:3] | |rs1 latexmath:[$'$] | |
-|uimm[2latexmath:[$\vert$]6] | |rd latexmath:[$'$] | | |00 |C.LW
+!001!uimm[5:4|8] !rs1 l' !uimm[7:6] !rd' !00 !C.LQ _(RV128)_
 
-|011|uimm[5:3] | |rs1 latexmath:[$'$] | |
-|uimm[2latexmath:[$\vert$]6] | |rd latexmath:[$'$] | | |00 |C.FLW
-_(RV32)_
+!010!uimm[5:3] !rs1 l'  !uimm[2|6] !rd' !00 !C.LW
 
-|011|uimm[5:3] | |rs1 latexmath:[$'$] | | |uimm[7:6] |
-|rd latexmath:[$'$] | | |00 |C.LD _(RV64/128)_
+!011!uimm[5:3] !rs1 l'  !uimm|6] !rd' !00 !C.FLW _(RV32)_
 
-|100|— | | | | | | | | | |00 |_Reserved_
+!011!uimm[5:3] !rs1 l'  !uimm[7:6] !rd'  !00 !C.LD _(RV64/128)_
 
-|101|uimm[5:3] | |rs1 latexmath:[$'$] | | |uimm[7:6] |
-|rs2 latexmath:[$'$] | | |00 |C.FSD _(RV32/64)_
+!100 4+!— !00 !_Reserved_
 
-|101 |uimm[5:4latexmath:[$\vert$]8] | |rs1 latexmath:[$'$] | |
-|uimm[7:6] | |rs2 latexmath:[$'$] | | |00 |C.SQ _(RV128)_
+!101!uimm[5:3] !rs1 l'  !uimm[7:6]  !rs2'  !00 !C.FSD _(RV32/64)_
 
-|110|uimm[5:3] | |rs1 latexmath:[$'$] | |
-|uimm[2latexmath:[$\vert$]6] | |rs2 latexmath:[$'$] | | |00 |C.SW
+!101 !uimm[5:4|8]  !rs1 l'  !uimm[7:6]  !rs2'  !00 !C.SQ _(RV128)_
 
-|111|uimm[5:3] | |rs1 latexmath:[$'$] | |
-|uimm[2 latexmath:[$\vert$]6] | |rs2 latexmath:[$'$] | | |00 |C.FSW
-_(RV32)_
+!110!uimm[5:3]  !rs1 l' ! uimm[2|6]  !rs2'  !00 !C.SW
 
-|111|uimm[5:3] | |rs1 latexmath:[$'$] | | |uimm[7:6] |
-|rs2 latexmath:[$'$] | | |00 |C.SD _(RV64/128)_
+!111!uimm[5:3]  !rs1 l'  !uimm[2|6]  !rs2'  !00 !C.FSW _(RV32)_
 
-|===
+!111!uimm[5:3] !rs1 l' !uimm[7:6]  !rs2' !00 !C.SD _(RV64/128)_
+
+!===
 
 [[rvc-instr-table1]]
 .Instruction listing for RVC, Quadrant 1
-//[cols="<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<",]
-|===
+[%header,format+DSV,separator=!,cols="2,3,2,2,2,2,2,6"]
+!===
 
-|000  |nzimm[5] |0 | | | | |nzimm[4:0] | | | | |01 | |C.NOP _(HINT,
-nzimm latexmath:[$\neq$]0)_
+! 15 14 13 ! 12 2+! 11 10 9 8 7 2+! 6 5 4 3 2 ! 1 0 !
 
-|000  |nzimm[5] |rs1/rdlatexmath:[$\neq$]0 | | | | |nzimm[4:0] | |
-| | |01 | |C.ADDI _(HINT, nzimm=0)_
+!000  !nzimm[5] 2+!0 2+!nzimm[4:0] !01 !C.NOP _(HINT,nzimm &#8800;0)_
 
-|001 | |
-|imm[11latexmath:[$\vert$]4latexmath:[$\vert$]9:8latexmath:[$\vert$]10latexmath:[$\vert$]6latexmath:[$\vert$]7latexmath:[$\vert$]3:1latexmath:[$\vert$]5]
-| | | | | | | | | | |01 | |C.JAL _(RV32)_
+!000  !nzimm[5] 2+!rs1/rd&#8800;0 2+!nzimm[4:0]  !01 !C.ADDI _(HINT, nzimm=0)_
 
-|001  |imm[5] |rs1/rd latexmath:[$\neq$]0 | | | | |imm[4:0] | | | |
-|01 | |C.ADDIW _(RV64/128; RES, rd=0)_
+!001 5+!imm[11|4|9:8|10|6|7|3:1|5]  !01 !C.JAL _(RV32)_
 
-|010  |imm[5] |rdlatexmath:[$\neq$]0 | | | | |imm[4:0] | | | | |01
-| |C.LI _(HINT, rd=0)_
+!001  !imm[5] 2+!rs1/rd &#8800;0 2+!imm[4:0]!01 !C.ADDIW _(RV64/128; RES, rd=0)_
 
-|011  |nzimm[9] |2 | | | |
-|nzimm[4 latexmath:[$\vert$]6latexmath:[$\vert$]8:7latexmath:[$\vert$]5]
-| | | | |01 | |C.ADDI16SP _(RES, nzimm=0)_
+!010  !imm[5] 2+!rd&#8800;0 2+!imm[4:0] !01 !C.LI _(HINT, rd=0)_
 
-|011  |nzimm[17] |rd latexmath:[$\neq$]latexmath:[$\{0,2\}$] | | | |
-|nzimm[16:12] | | | | |01 | |C.LUI _(RES, nzimm=0; HINT, rd=0)_
+!011  !nzimm[9] 2+!2 2+!nzimm[4|6|8:7|5] !01 !C.ADDI16SP _(RES, nzimm=0)_
 
-|100  |nzuimm[5] |00 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | |
-|nzuimm[4:0] | | | | |01 | |C.SRLI _(RV32 Custom, nzuimm[5]=1)_
+!011  !nzimm[17] 2+!rd &#8800;{0,2} 2+!nzimm[16:12] !01 !C.LUI _(RES, nzimm=0; HINT, rd=0)_
 
-|100  |0 |00 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | | |0 | | |
-| |01 | |C.SRLI64 _(RV128; RV32/64 HINT)_
+!100  !nzuimm[5] !00 !rs1'/rd' 2+!nzuimm[4:0]!01 !C.SRLI _(RV32 Custom, nzuimm[5]=1)_
 
-|100  |nzuimm[5] |01 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | |
-|nzuimm[4:0] | | | | |01 | |C.SRAI _(RV32 Custom, nzuimm[5]=1)_
+!100  !0 !00 !rs1'/rd l'  2+!0  !01 !C.SRLI64 _(RV128; RV32/64 HINT)_
 
-|100 |0 |01 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | | |0 | | |
-| |01 | |C.SRAI64 _(RV128; RV32/64 HINT)_
+!100  !nzuimm[5] !01 !rs1'/rd' 2+!nzuimm[4:0] !01 !C.SRAI _(RV32 Custom, nzuimm[5]=1)_
 
-|100  |imm[5] |10 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | |
-|imm[4:0] | | | | |01 | |C.ANDI
+!100 !0 !01 !rs1'/rd' 2+!0  !01 !C.SRAI64 _(RV128; RV32/64 HINT)_
 
-|100  |0 |11 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | | |00 |
-|rs2 latexmath:[$'$] | | |01 | |C.SUB
+!100  !imm[5] !10 !rs1 l'/rd' 2+!imm[4:0] !01 !_C.ANDI_
 
-|100  |0 |11 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | | |01 |
-|rs2 latexmath:[$'$] | | |01 | |C.XOR
+!100  !0 !11 !rs1'/rd' !00 ! rs2' !01 !_C.SUB_
 
-|100  |0 |11 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | | |10 |
-|rs2 latexmath:[$'$] | | |01 | |C.OR
+!100  !0 !11 !rs1'/rd' !01  !rs2 l' !01 !_C.XOR_
 
-|100  |0 |11 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | | |11 |
-|rs2 latexmath:[$'$] | | |01 | |C.AND
+!100  !0 !11 !rs1'/rd' !10  !rs2 l' !01 !_C.OR_
 
-|100  |1 |11 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | | |00 |
-|rs2 latexmath:[$'$] | | |01 | |C.SUBW _(RV64/128; RV32 RES)_
+!100  !0 !11 !rs1'/rd' !11  !rs2 l' !01 !_C.AND_
 
-|100  |1 |11 | |rs1 latexmath:[$'$]/rd latexmath:[$'$] | | |01 |
-|rs2 latexmath:[$'$] | | |01 | |C.ADDW _(RV64/128; RV32 RES)_
+!100  !1 !11 !rs1'/rd' !00  !rs2 l' !01 !_C.SUBW (RV64/128; RV32 RES)_
 
-|100  |1 |11 | |— | | |10 | |— | | |01 | |_Reserved_
+!100  !1 !11 !rs1'/rd' !01  !rs2 l' !01 !_C.ADDW (RV64/128; RV32 RES)_
 
-|100  |1 |11 | |— | | |11 | |— | | |01 | |_Reserved_
+!100  !1 !11 !—  !10 !— !01 !_Reserved_
 
-|101
-|imm[11 latexmath:[$\vert$]4latexmath:[$\vert$]9:8latexmath:[$\vert$]10latexmath:[$\vert$]6latexmath:[$\vert$]7latexmath:[$\vert$]3:1latexmath:[$\vert$]5]
-| | | | | | | | | | |01 | |C.J
+!100  !1 !11 !—  !11 !— !01 !_Reserved_
 
-|110  |imm[8latexmath:[$\vert$]4:3] | | |rs1 latexmath:[$'$] | |
-|imm[7:6 latexmath:[$\vert$]2:1 latexmath:[$\vert$]5] | | | | |01 |
-|C.BEQZ
+!101 5+!imm[11 |4|9:8|10|6|7|3:1|5] !01 !C.J
 
-|111  |imm[8 latexmath:[$\vert$]4:3] | | |rs1 latexmath:[$'$] | |
-|imm[7:6 latexmath:[$\vert$]2:1 latexmath:[$\vert$]5] | | | | |01 |
-|C.BNEZ
+!110  2+!imm[8|4:3] !rs1' 2+!imm[7:6 |2:1|5] !01 !C.BEQZ
 
-|===
+!111  2+!imm[8 |4:3] !rs1' 2+!imm[7:6 |2:1 |5] !01 !C.BNEZ
+
+!===
 
 [[rvc-instr-table2]]
 .Instruction listing for RVC, Quadrant 2
-//[cols="<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<,<",]
-|===
+[%header,format+DSV,separator=!,cols="10%,14%,14%,16%,5%,41%"]
+!===
+!15 14 13 !12 !11 10 9 8 7! 6 5 4 3 2 !1 0 !
+
+!000! nzuimm[5]! rs1/rd̸=0 ! nzuimm[4:0] ! 10 ! C.SLLI _(HINT, rd=0; RV32 Custom, nzuimm[5]=1)_
 
-|000  |nzuimm[5] |rs1/rd latexmath:[$\neq$]0 | | | | |nzuimm[4:0] |
-| | | |10 | |C.SLLI _(HINT, rd=0; RV32 Custom, nzuimm[5]=1)_
+!000! 0! rs1/rd̸=0! 0! 10 !C.SLLI64 _(RV128; RV32/64 HINT; HINT, rd=0)_
 
-|000  |0 |rs1/rd latexmath:[$\neq$]0 | | | | |0 | | | | |10 |
-|C.SLLI64 _(RV128; RV32/64 HINT; HINT, rd=0)_
+!001! uimm[5]! rd! uimm[4:3|8:6]! 10 !C.FLDSP _(RV32/64)_
 
-|001  |uimm[5] |rd | | | | |uimm[4:3latexmath:[$\vert$]8:6] | | | |
-|10 | |C.FLDSP _(RV32/64)_
+!001! uimm[5]! rd̸=0! uimm[4|9:6]! 10! C.LQSP _(RV128; RES, rd=0)_
 
-|001  |uimm[5] |rdlatexmath:[$\neq$]0 | | | |
-|uimm[4latexmath:[$\vert$]9:6] | | | | |10 | |C.LQSP _(RV128; RES,
-rd=0)_
+!010! uimm[5]! rd̸=0! uimm[4:2|7:6] !10 !C.LWSP _(RES, rd=0)_
 
-|010  |uimm[5] |rdlatexmath:[$\neq$]0 | | | |
-|uimm[4:2latexmath:[$\vert$]7:6] | | | | |10 | |C.LWSP _(RES, rd=0)_
+!011! uimm[5]! rd! uimm[4:2|7:6]! 10! C.FLWSP _(RV32)_
 
-|011  |uimm[5] |rd | | | | |uimm[4:2latexmath:[$\vert$]7:6] | | | |
-|10 | |C.FLWSP _(RV32)_
+!011! uimm[5]! rd̸=0! uimm[4:3|8:6]! 10! C.LDSP _(RV64/128; RES, rd=0)_
 
-|011 |uimm[5] |rdlatexmath:[$\neq$]0 | | | |
-|uimm[4:3latexmath:[$\vert$]8:6] | | | | |10 | |C.LDSP _(RV64/128; RES,
-rd=0)_
+!100! 0! rs1 &#8800; 0! 0 !10 ! C.JR _(RES, rs1=0)_
 
-|100  |0 |rs1latexmath:[$\neq$]0 | | | | |0 | | | | |10 | |C.JR
-_(RES, rs1=0)_
+!100! 0! rd &#8800; 0! rs2 &#8800; 0 !10 ! C.MV _(HINT, rd=0)_
 
-|100  |0 |rdlatexmath:[$\neq$]0 | | | | |rs2latexmath:[$\neq$]0 | |
-| | |10 | |C.MV _(HINT, rd=0)_
+!100! 1! 0 !0 !10 ! C.EBREAK
 
-|100 |1 |0 | | | | |0 | | | | |10 | |C.EBREAK
+!100! 1! rs1 &#8800; =0! 0 ! 10 ! C.JALR
 
-|100  |1 |rs1latexmath:[$\neq$]0 | | | | |0 | | | | |10 | |C.JALR
+!100! 1! rs1/rd̸=0 !rs2 &#8800; 0! 10! C.ADD _(HINT, rd=0)_
 
-|100  | |1 |rs1/rdlatexmath:[$\neq$]0 | | | | |rs2latexmath:[$\neq$]0
-| | | | |10 | |C.ADD _(HINT, rd=0)_
+!101 2+! uimm[5:3|8:6]! rs2! 10! C.FSDSP _(RV32/64)_
 
-|101  |uimm[5:3latexmath:[$\vert$]8:6] | | | | | |rs2 | | | | |10 |
-|C.FSDSP _(RV32/64)_
+!101 2+! uimm[5:4|9:6]! rs2 ! 10! C.SQSP _(RV128)_
 
-|101  |uimm[5:4latexmath:[$\vert$]9:6] | | | | | |rs2 | | | | |10 |
-|C.SQSP _(RV128)_
+!110 2+! uimm[5:2|7:6]! rs2 ! 10! C.SWSP
 
-|110  |uimm[5:2latexmath:[$\vert$]7:6] | | | | | |rs2 | | | | |10 |
-|C.SWSP
+!111 2+! uimm[5:2|7:6]! rs2 ! 10 !C.FSWSP _(RV32)_
+!111 2+! uimm[5:3|8:6]! rs2 ! 10 !C.SDSP _(RV64/128)_
+!===
 
-|111  |uimm[5:2latexmath:[$\vert$]7:6] | | | | | |rs2 | | | | |10 |
-|C.FSWSP _(RV32)_
 
-|111  |uimm[5:3latexmath:[$\vert$]8:6] | | | | | |rs2 | | | | |10 |
-|C.SDSP _(RV64/128)_
 
 |===
diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.adoc
index 88db337..60c6d54 100644
--- a/src/images/wavedrom/cr-register.adoc
+++ b/src/images/wavedrom/cr-register.adoc
@@ -56,7 +56,7 @@
   {bits: 2,  name: 'op',     type: 8},
   {bits: 11, name: 'jump target', type: 3},
   {bits: 3,  name: 'funct3', type: 8},
-],
+]
 
 }
 ....
@@ -67,7 +67,7 @@
 //  compact: true,
 //  bits: 16 * 9, lanes: 9,
 //  margin: {right: width / 4},
-// label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS : Store', 'CA : //Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']}
+// label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS //: Store', 'CA : //Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']}
 //}
 
 
diff --git a/src/images/wavedrom/reg-based-ldnstr.adoc b/src/images/wavedrom/reg-based-ldnstr.adoc
new file mode 100644
index 0000000..d073697
--- /dev/null
+++ b/src/images/wavedrom/reg-based-ldnstr.adoc
@@ -0,0 +1,14 @@
+//Register-Based loads and Stores
+//needs fix
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op', attr: ['2', 'CD', 'CD', 'CD', 'CD', 'CD'], type: 8},
+  {bits: 4, name: 'rd',  attr: ['3', 'dest', 'dest','dest','dest','dest'], type: 3},
+  {bits: 2, name: 'imm', attr:['2', 'offest[2|6]', 'offest[7:6]', 'offest[7:6]', 'offest[2|6]', 'offest[7:6]'], type: 2},
+  {bits: 4, name: 'rs2 `', attr: ['3', 'base', 'base', 'base', 'base', 'base'], type: 2},
+  {bits: 4, name: 'imm',  attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]'], type: 3},
+  {bits: 4, name: 'funct3',  attr: ['3', 'C|W', 'C|D', 'C|Q', 'CF|W', 'CF|D'], type: 8},
+]}
+....
diff --git a/src/images/wavedrom/sp-base-ls-2.adoc b/src/images/wavedrom/sp-base-ls-2.adoc
index 5ec43c1..a5c05f0 100644
--- a/src/images/wavedrom/sp-base-ls-2.adoc
+++ b/src/images/wavedrom/sp-base-ls-2.adoc
@@ -2,8 +2,8 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 2, name: 'op',     type: 8, attr: 'C2'},
-  {bits: 5, name: 'rs2',    type: 4, attr: 'src'},
+  {bits: 2, name: 'op',     type: 8, attr: ['C2','C2','C2','C2','C2']},
+  {bits: 5, name: 'rs2',    type: 4, attr: ['src', 'src', 'src', 'src', 'src']},
   {bits: 6, name: 'imm',    type: 3, attr: ['offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]', 'offset[5:3|8:6]']},
   {bits: 3, name: 'funct3', type: 8, attr: ['C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']},
 ], config: {bits: 16}}
diff --git a/src/riscv-isa-unpr-conv-review.adoc b/src/riscv-isa-unpr-conv-review.adoc
index 76940b7..c202308 100644
--- a/src/riscv-isa-unpr-conv-review.adoc
+++ b/src/riscv-isa-unpr-conv-review.adoc
@@ -3,7 +3,7 @@
 :description: Volume I: Unprivileged ISA
 :company: RISC-V.org
 //:authors: Editors: Andrew waterman, Krste Asanovic, SiFive, Inc., CS Division, EECS Department, University of California, Berkeley
-:revdate: 09/2021
+:revdate: 10/2021
 :revnumber: Convert pre
 :revremark: Pre-release version
 //development: assume everything can change
@@ -36,7 +36,7 @@
 :toclevels: 4
 :source-highlighter: pygments
 ifdef::backend-pdf[]
-:source-highlighter: coderay
+:source-highlighter: rouge
 endif::[]
 :table-caption: Table
 :figure-caption: Figure
diff --git a/src/riscv-isa-unpr-conv-review.pdf b/src/riscv-isa-unpr-conv-review.pdf
index 917caf4..2c81497 100644
--- a/src/riscv-isa-unpr-conv-review.pdf
+++ b/src/riscv-isa-unpr-conv-review.pdf