Improve rd'/rs1'/rs2' typesetting

2 files changed, 122 insertions, 118 deletions

diff --git a/src/c.tex b/src/c.tex
index d0e1333..1f4869e 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -234,6 +234,10 @@ For many RVC instructions, zero-valued immediates are disallowed and
 free up encoding space for other instructions requiring fewer operand
 bits.
 
+\newcommand{\rdprime}{rd\,$'$}
+\newcommand{\rsoneprime}{rs1\,$'$}
+\newcommand{\rstwoprime}{rs2\,$'$}
+
 \begin{table}[h]
 {
 \begin{small}
@@ -284,40 +288,40 @@ CSS & Stack-relative Store &
 CIW & Wide Immediate &
 \multicolumn{3}{|c|}{funct3} &
 \multicolumn{8}{c|}{imm} &
-\multicolumn{3}{c|}{rd$'$} &
+\multicolumn{3}{c|}{\rdprime} &
 \multicolumn{2}{c|}{op} \\
 \cline{3-18}
 
 CL & Load &
 \multicolumn{3}{|c|}{funct3} &
 \multicolumn{3}{c|}{imm} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{imm} &
-\multicolumn{3}{c|}{rd$'$} &
+\multicolumn{3}{c|}{\rdprime} &
 \multicolumn{2}{c|}{op} \\
 \cline{3-18}
 
 CS & Store &
 \multicolumn{3}{|c|}{funct3} &
 \multicolumn{3}{c|}{imm} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{imm} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{op} \\
 \cline{3-18}
 
 CA & Arithmetic &
 \multicolumn{6}{|c|}{funct6} &
-\multicolumn{3}{c|}{rd$'$/rs1$'$} &
+\multicolumn{3}{c|}{\rdprime/\rsoneprime} &
 \multicolumn{2}{c|}{funct2} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{op} \\
 \cline{3-18}
 
 CB & Branch &
 \multicolumn{3}{|c|}{funct3} &
 \multicolumn{3}{c|}{offset} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{5}{c|}{offset} &
 \multicolumn{2}{c|}{op} \\
 \cline{3-18}
@@ -351,7 +355,7 @@ Floating-Point Register ABI Name    & {\tt fs0}  &  {\tt fs1} &  {\tt fa0} &  {\
 \end{tabular}
 \end{center}
 }
-\caption{Registers specified by the three-bit {\em rs1$'$}, {\em rs2$'$}, and {\em rd$'$} fields of the CIW, CL, CS, CA, and CB formats.}
+\caption{Registers specified by the three-bit {\em \rsoneprime}, {\em \rstwoprime}, and {\em \rdprime} fields of the CIW, CL, CS, CA, and CB formats.}
 \label{registers}
 \end{table}
 
@@ -527,9 +531,9 @@ attain the greatest code size reduction.
 \hline
 \multicolumn{1}{|c|}{funct3} &
 \multicolumn{1}{c|}{imm} &
-\multicolumn{1}{c|}{rs1$'$} &
+\multicolumn{1}{c|}{\rsoneprime} &
 \multicolumn{1}{c|}{imm} &
-\multicolumn{1}{c|}{rd$'$} &
+\multicolumn{1}{c|}{\rdprime} &
 \multicolumn{1}{c|}{op} \\
 \hline
 3 & 3 & 3 & 2 & 3 & 2 \\
@@ -542,34 +546,34 @@ C.FLD& offset[5:3] & base & offset[7:6] & dest & C0 \\
 \end{center}
 These instructions use the CL format.
 
-C.LW loads a 32-bit value from memory into register {\em rd$'$}.  It computes
+C.LW loads a 32-bit value from memory into register {\em \rdprime}.  It computes
 an effective address by adding the {\em zero}-extended offset, scaled by 4, to
-the base address in register {\em rs1$'$}.
-It expands to {\tt lw rd$'$, offset[6:2](rs1$'$)}.
+the base address in register {\em \rsoneprime}.
+It expands to {\tt lw \rdprime, offset[6:2](\rsoneprime)}.
 
 C.LD is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into
-register {\em rd$'$}.  It computes an effective address by adding the {\em
+register {\em \rdprime}.  It computes an effective address by adding the {\em
 zero}-extended offset, scaled by 8, to the base address in register {\em
-rs1$'$}.
-It expands to {\tt ld rd$'$, offset[7:3](rs1$'$)}.
+\rsoneprime}.
+It expands to {\tt ld \rdprime, offset[7:3](\rsoneprime)}.
 
 C.LQ is an RV128C-only instruction that loads a 128-bit value from memory into
-register {\em rd$'$}.  It computes an effective address by adding the {\em
+register {\em \rdprime}.  It computes an effective address by adding the {\em
 zero}-extended offset, scaled by 16, to the base address in register {\em
-rs1$'$}.
-It expands to {\tt lq rd$'$, offset[8:4](rs1$'$)}.
+\rsoneprime}.
+It expands to {\tt lq \rdprime, offset[8:4](\rsoneprime)}.
 
 C.FLW is an RV32FC-only instruction that loads a single-precision
-floating-point value from memory into floating-point register {\em rd$'$}.  It
+floating-point value from memory into floating-point register {\em \rdprime}.  It
 computes an effective address by adding the {\em zero}-extended offset, scaled
-by 4, to the base address in register {\em rs1$'$}.  It expands to {\tt flw
-rd$'$, offset[6:2](rs1$'$)}.
+by 4, to the base address in register {\em \rsoneprime}.  It expands to {\tt flw
+\rdprime, offset[6:2](\rsoneprime)}.
 
 C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision
-floating-point value from memory into floating-point register {\em rd$'$}.  It
+floating-point value from memory into floating-point register {\em \rdprime}.  It
 computes an effective address by adding the {\em zero}-extended offset, scaled
-by 8, to the base address in register {\em rs1$'$}.  It expands to {\tt fld
-rd$'$, offset[7:3](rs1$'$)}.
+by 8, to the base address in register {\em \rsoneprime}.  It expands to {\tt fld
+\rdprime, offset[7:3](\rsoneprime)}.
 
 \begin{center}
 \begin{tabular}{S@{}S@{}S@{}Y@{}S@{}Y}
@@ -583,9 +587,9 @@ rd$'$, offset[7:3](rs1$'$)}.
 \hline
 \multicolumn{1}{|c|}{funct3} &
 \multicolumn{1}{c|}{imm} &
-\multicolumn{1}{c|}{rs1$'$} &
+\multicolumn{1}{c|}{\rsoneprime} &
 \multicolumn{1}{c|}{imm} &
-\multicolumn{1}{c|}{rs2$'$} &
+\multicolumn{1}{c|}{\rstwoprime} &
 \multicolumn{1}{c|}{op} \\
 \hline
 3 & 3 & 3 & 2 & 3 & 2 \\
@@ -598,34 +602,34 @@ C.FSD& offset[5:3] & base & offset[7:6] & src & C0 \\
 \end{center}
 These instructions use the CS format.
 
-C.SW stores a 32-bit value in register {\em rs2$'$} to memory.  It computes an
+C.SW stores a 32-bit value in register {\em \rstwoprime} to memory.  It computes an
 effective address by adding the {\em zero}-extended offset, scaled by 4, to
-the base address in register {\em rs1$'$}.
-It expands to {\tt sw rs2$'$, offset[6:2](rs1$'$)}.
+the base address in register {\em \rsoneprime}.
+It expands to {\tt sw \rstwoprime, offset[6:2](\rsoneprime)}.
 
 C.SD is an RV64C/RV128C-only instruction that stores a 64-bit value in
-register {\em rs2$'$} to memory.  It computes an effective address by adding
+register {\em \rstwoprime} to memory.  It computes an effective address by adding
 the {\em zero}-extended offset, scaled by 8, to the base address in register
-{\em rs1$'$}.
-It expands to {\tt sd rs2$'$, offset[7:3](rs1$'$)}.
+{\em \rsoneprime}.
+It expands to {\tt sd \rstwoprime, offset[7:3](\rsoneprime)}.
 
 C.SQ is an RV128C-only instruction that stores a 128-bit value in register
-{\em rs2$'$} to memory.  It computes an effective address by adding the {\em
+{\em \rstwoprime} to memory.  It computes an effective address by adding the {\em
 zero}-extended offset, scaled by 16, to the base address in register {\em
-rs1$'$}.
-It expands to {\tt sq rs2$'$, offset[8:4](rs1$'$)}.
+\rsoneprime}.
+It expands to {\tt sq \rstwoprime, offset[8:4](\rsoneprime)}.
 
 C.FSW is an RV32FC-only instruction that stores a single-precision
-floating-point value in floating-point register {\em rs2$'$} to memory.  It
+floating-point value in floating-point register {\em \rstwoprime} to memory.  It
 computes an effective address by adding the {\em zero}-extended offset, scaled
-by 4, to the base address in register {\em rs1$'$}.  It expands to {\tt fsw
-rs2$'$, offset[6:2](rs1$'$)}.
+by 4, to the base address in register {\em \rsoneprime}.  It expands to {\tt fsw
+\rstwoprime, offset[6:2](\rsoneprime)}.
 
 C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision
-floating-point value in floating-point register {\em rs2$'$} to memory.  It
+floating-point value in floating-point register {\em \rstwoprime} to memory.  It
 computes an effective address by adding the {\em zero}-extended offset, scaled
-by 8, to the base address in register {\em rs1$'$}.  It expands to {\tt fsd
-rs2$'$, offset[7:3](rs1$'$)}.
+by 8, to the base address in register {\em \rsoneprime}.  It expands to {\tt fsd
+\rstwoprime, offset[7:3](\rsoneprime)}.
 
 \section{Control Transfer Instructions}
 
@@ -706,7 +710,7 @@ rather than 4 as in the base ISA, but supporting both offsets of 2 and
 \hline
 \multicolumn{1}{|c|}{funct3} &
 \multicolumn{1}{c|}{imm} &
-\multicolumn{1}{c|}{rs1$'$} &
+\multicolumn{1}{c|}{\rsoneprime} &
 \multicolumn{1}{c|}{imm} &
 \multicolumn{1}{c|}{op} \\
 \hline
@@ -720,11 +724,11 @@ These instructions use the CB format.
 C.BEQZ performs conditional control transfers.  The offset is sign-extended
 and added to the {\tt pc} to form the branch target address.  It can
 therefore target a $\pm$\wunits{256}{B} range.  C.BEQZ takes the branch if the
-value in register {\em rs1$'$} is zero.  It expands to {\tt beq rs1$'$, x0,
+value in register {\em \rsoneprime} is zero.  It expands to {\tt beq \rsoneprime, x0,
 offset[8:1]}.
 
-C.BNEZ is defined analogously, but it takes the branch if {\em rs1$'$} contains
-a nonzero value.  It expands to {\tt bne rs1$'$, x0, offset[8:1]}.
+C.BNEZ is defined analogously, but it takes the branch if {\em \rsoneprime} contains
+a nonzero value.  It expands to {\tt bne \rsoneprime, x0, offset[8:1]}.
 
 \section{Integer Computational Instructions}
 
@@ -829,7 +833,7 @@ is always 16-byte aligned.
 \hline
 \multicolumn{1}{|c|}{funct3} &
 \multicolumn{1}{c|}{imm} &
-\multicolumn{1}{c|}{rd$'$} &
+\multicolumn{1}{c|}{\rdprime} &
 \multicolumn{1}{c|}{op} \\
 \hline
 3 & 8 & 3 & 2 \\
@@ -839,9 +843,9 @@ C.ADDI4SPN & nzuimm[5:4$\vert$9:6$\vert$2$\vert$3] & dest & C0 \\
 
 C.ADDI4SPN is a CIW-format instruction that adds a {\em zero}-extended
 non-zero immediate, scaled by 4, to the stack pointer, {\tt x2}, and
-writes the result to {\tt rd$'$}.  This instruction is used
+writes the result to {\tt \rdprime}.  This instruction is used
 to generate pointers to stack-allocated variables, and expands to
-{\tt addi rd$'$, x2, nzuimm[9:2]}.
+{\tt addi \rdprime, x2, nzuimm[9:2]}.
 
 
 \vspace{-0.4in}
@@ -888,7 +892,7 @@ to encode a shift of 64.  C.SLLI expands into {\tt slli rd, rd,
 \multicolumn{1}{|c|}{funct3} &
 \multicolumn{1}{c|}{shamt[5]} &
 \multicolumn{1}{|c|}{funct2} &
-\multicolumn{1}{c|}{rd$'$/rs1$'$} &
+\multicolumn{1}{c|}{\rdprime/\rsoneprime} &
 \multicolumn{1}{c|}{shamt[4:0]} &
 \multicolumn{1}{c|}{op} \\
 \hline
@@ -899,19 +903,19 @@ C.SRAI  & shamt[5] & C.SRAI & dest & shamt[4:0] & C1 \\
 \end{center}
 
 C.SRLI is a CB-format instruction that performs a logical right shift
-of the value in register {\em rd$'$} then writes the result to {\em rd$'$}.
+of the value in register {\em \rdprime} then writes the result to {\em \rdprime}.
 The shift amount is encoded in the {\em shamt} field, where {\em
   shamt[5]} must be zero for RV32C.  For RV32C and RV64C, the shift
 amount must be non-zero.  For RV128C, a shift amount of zero is used
 to encode a shift of 64.  Furthermore, the shift amount is sign-extended
 for RV128C, and so the legal shift amounts are 1--31, 64, and 96--127.
-C.SRLI expands into {\tt srli rd$'$, rd$'$, shamt[5:0]},
+C.SRLI expands into {\tt srli \rdprime, \rdprime, shamt[5:0]},
 except for RV128C with {\tt shamt=0}, which expands to
-{\tt srli rd$'$, rd$'$, 64}.
+{\tt srli \rdprime, \rdprime, 64}.
 
 C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic
 right shift.
-C.SRAI expands to {\tt srai rd$'$, rd$'$, shamt[5:0]}.
+C.SRAI expands to {\tt srai \rdprime, \rdprime, shamt[5:0]}.
 
 \begin{commentary}
 Left shifts are usually more frequent than right shifts, as left
@@ -940,7 +944,7 @@ point as RV32C and RV64C, to allow evaluation of typical usage of
 \multicolumn{1}{|c|}{funct3} &
 \multicolumn{1}{c|}{imm[5]} &
 \multicolumn{1}{|c|}{funct2} &
-\multicolumn{1}{c|}{rd$'$/rs1$'$} &
+\multicolumn{1}{c|}{\rdprime/\rsoneprime} &
 \multicolumn{1}{c|}{imm[4:0]} &
 \multicolumn{1}{c|}{op} \\
 \hline
@@ -950,9 +954,9 @@ C.ANDI  & imm[5] & C.ANDI & dest & imm[4:0] & C1 \\
 \end{center}
 
 C.ANDI is a CB-format instruction that computes the bitwise AND of
-of the value in register {\em rd$'$} and the sign-extended 6-bit immediate,
-then writes the result to {\em rd$'$}.
-C.ANDI expands to {\tt andi rd$'$, rd$'$, imm[5:0]}.
+the value in register {\em \rdprime} and the sign-extended 6-bit immediate,
+then writes the result to {\em \rdprime}.
+C.ANDI expands to {\tt andi \rdprime, \rdprime, imm[5:0]}.
 
 \subsection*{Integer Register-Register Operations}
 \vspace{-0.4in}
@@ -1000,9 +1004,9 @@ result to register {\em rd}.  C.ADD expands into {\tt add rd, rd, rs2}.
 \instbitrange{1}{0} \\
 \hline
 \multicolumn{1}{|c|}{funct6} &
-\multicolumn{1}{c|}{rd$'$/rs1$'$} &
+\multicolumn{1}{c|}{\rdprime/\rsoneprime} &
 \multicolumn{1}{c|}{funct2} &
-\multicolumn{1}{c|}{rs2$'$} &
+\multicolumn{1}{c|}{\rstwoprime} &
 \multicolumn{1}{c|}{op} \\
 \hline
 6 & 3 & 2 & 3 & 2 \\
@@ -1017,31 +1021,31 @@ C.SUBW & dest & C.SUBW & src & C1 \\
 
 These instructions use the CA format.
 
-C.AND computes the bitwise AND of the values in registers {\em rd$'$}
-and {\em rs2$'$}, then writes the result to register {\em rd$'$}.
-C.AND expands into {\tt and rd$'$, rd$'$, rs2$'$}.
+C.AND computes the bitwise AND of the values in registers {\em \rdprime}
+and {\em \rstwoprime}, then writes the result to register {\em \rdprime}.
+C.AND expands into {\tt and \rdprime, \rdprime, \rstwoprime}.
 
-C.OR computes the bitwise OR of the values in registers {\em rd$'$}
-and {\em rs2$'$}, then writes the result to register {\em rd$'$}.
-C.OR expands into {\tt or rd$'$, rd$'$, rs2$'$}.
+C.OR computes the bitwise OR of the values in registers {\em \rdprime}
+and {\em \rstwoprime}, then writes the result to register {\em \rdprime}.
+C.OR expands into {\tt or \rdprime, \rdprime, \rstwoprime}.
 
-C.XOR computes the bitwise XOR of the values in registers {\em rd$'$}
-and {\em rs2$'$}, then writes the result to register {\em rd$'$}.
-C.XOR expands into {\tt xor rd$'$, rd$'$, rs2$'$}.
+C.XOR computes the bitwise XOR of the values in registers {\em \rdprime}
+and {\em \rstwoprime}, then writes the result to register {\em \rdprime}.
+C.XOR expands into {\tt xor \rdprime, \rdprime, \rstwoprime}.
 
-C.SUB subtracts the value in register {\em rs2$'$} from the value in
-register {\em rd$'$}, then writes the result to register {\em rd$'$}.
-C.SUB expands into {\tt sub rd$'$, rd$'$, rs2$'$}.
+C.SUB subtracts the value in register {\em \rstwoprime} from the value in
+register {\em \rdprime}, then writes the result to register {\em \rdprime}.
+C.SUB expands into {\tt sub \rdprime, \rdprime, \rstwoprime}.
 
 C.ADDW is an RV64C/RV128C-only instruction that adds the values in
-registers {\em rd$'$} and {\em rs2$'$}, then sign-extends the lower
-32 bits of the sum before writing the result to register {\em rd$'$}.
-C.ADDW expands into {\tt addw rd$'$, rd$'$, rs2$'$}.
+registers {\em \rdprime} and {\em \rstwoprime}, then sign-extends the lower
+32 bits of the sum before writing the result to register {\em \rdprime}.
+C.ADDW expands into {\tt addw \rdprime, \rdprime, \rstwoprime}.
 
 C.SUBW is an RV64C/RV128C-only instruction that subtracts the value in
-register {\em rs2$'$} from the value in register {\em rd$'$}, then
+register {\em \rstwoprime} from the value in register {\em \rdprime}, then
 sign-extends the lower 32 bits of the difference before writing the result
-to register {\em rd$'$}. C.SUBW expands into {\tt subw rd$'$, rd$'$, rs2$'$}.
+to register {\em \rdprime}. C.SUBW expands into {\tt subw \rdprime, \rdprime, \rstwoprime}.
 
 \begin{commentary}
 This group of six instructions do not provide large savings
diff --git a/src/rvc-instr-table.tex b/src/rvc-instr-table.tex
index ce7f6c5..ab365df 100644
--- a/src/rvc-instr-table.tex
+++ b/src/rvc-instr-table.tex
@@ -34,52 +34,52 @@
 &
 \multicolumn{3}{|c|}{000} &
 \multicolumn{8}{c|}{nzuimm[5:4$\vert$9:6$\vert$2$\vert$3]} &
-\multicolumn{3}{c|}{rd$'$} &
+\multicolumn{3}{c|}{\rdprime} &
 \multicolumn{2}{c|}{00} & C.ADDI4SPN {\em \tiny (RES, nzuimm=0)} \\
 \whline{2-17}
 
 &
 \multicolumn{3}{|c|}{001} &
 \multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{rd$'$} &
+\multicolumn{3}{c|}{\rdprime} &
 \multicolumn{2}{c|}{00} & C.FLD {\em \tiny (RV32/64)}\\
 \cline{2-17}
 
 &
 \multicolumn{3}{|c|}{001} &
 \multicolumn{3}{c|}{uimm[5:4$\vert$8]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{rd$'$} &
+\multicolumn{3}{c|}{\rdprime} &
 \multicolumn{2}{c|}{00} & C.LQ {\em \tiny (RV128)}\\
 \whline{2-17}
 
 &
 \multicolumn{3}{|c|}{010} &
 \multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[2$\vert$6]} &
-\multicolumn{3}{c|}{rd$'$} &
+\multicolumn{3}{c|}{\rdprime} &
 \multicolumn{2}{c|}{00} & C.LW \\
 \whline{2-17}
 
 &
 \multicolumn{3}{|c|}{011} &
 \multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[2$\vert$6]} &
-\multicolumn{3}{c|}{rd$'$} &
+\multicolumn{3}{c|}{\rdprime} &
 \multicolumn{2}{c|}{00} & C.FLW {\em \tiny (RV32)} \\
 \cline{2-17}
 
 &
 \multicolumn{3}{|c|}{011} &
 \multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{rd$'$} &
+\multicolumn{3}{c|}{\rdprime} &
 \multicolumn{2}{c|}{00} & C.LD {\em \tiny (RV64/128)}\\
 \whline{2-17}
 
@@ -92,45 +92,45 @@
 &
 \multicolumn{3}{|c|}{101} &
 \multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{00} & C.FSD {\em \tiny (RV32/64)}\\
 \cline{2-17}
 
 &
 \multicolumn{3}{|c|}{101} &
 \multicolumn{3}{c|}{uimm[5:4$\vert$8]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{00} & C.SQ {\em \tiny (RV128)}\\
 \whline{2-17}
 
 &
 \multicolumn{3}{|c|}{110} &
 \multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[2$\vert$6]} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{00} & C.SW \\
 \whline{2-17}
 
 &
 \multicolumn{3}{|c|}{111} &
 \multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[2$\vert$6]} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{00} & C.FSW {\em \tiny (RV32)} \\
 \cline{2-17}
 
 &
 \multicolumn{3}{|c|}{111} &
 \multicolumn{3}{c|}{uimm[5:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{2}{c|}{uimm[7:6]} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{00} & C.SD {\em \tiny (RV64/128)}\\
 \cline{2-17}
 
@@ -223,7 +223,7 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{nzuimm[5]} &
 \multicolumn{2}{c|}{00} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{5}{c|}{nzuimm[4:0]} &
 \multicolumn{2}{c|}{01} & C.SRLI {\em \tiny (RV32 NSE, nzuimm[5]=1)} \\
 \cline{2-17}
@@ -232,7 +232,7 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{0} &
 \multicolumn{2}{c|}{00} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{5}{c|}{0} &
 \multicolumn{2}{c|}{01} & C.SRLI64 {\em \tiny (RV128; RV32/64 HINT)} \\
 \cline{2-17}
@@ -241,7 +241,7 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{nzuimm[5]} &
 \multicolumn{2}{c|}{01} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{5}{c|}{nzuimm[4:0]} &
 \multicolumn{2}{c|}{01} & C.SRAI {\em \tiny (RV32 NSE, nzuimm[5]=1)} \\
 \cline{2-17}
@@ -250,7 +250,7 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{0} &
 \multicolumn{2}{c|}{01} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{5}{c|}{0} &
 \multicolumn{2}{c|}{01} & C.SRAI64 {\em \tiny (RV128; RV32/64 HINT)} \\
 \cline{2-17}
@@ -259,7 +259,7 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{imm[5]} &
 \multicolumn{2}{c|}{10} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{5}{c|}{imm[4:0]} &
 \multicolumn{2}{c|}{01} & C.ANDI \\
 \cline{2-17}
@@ -268,9 +268,9 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{0} &
 \multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{2}{c|}{00} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{01} & C.SUB \\
 \cline{2-17}
 
@@ -278,9 +278,9 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{0} &
 \multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{2}{c|}{01} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{01} & C.XOR \\
 \cline{2-17}
 
@@ -288,9 +288,9 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{0} &
 \multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{2}{c|}{10} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{01} & C.OR \\
 \cline{2-17}
 
@@ -298,9 +298,9 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{0} &
 \multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{01} & C.AND \\
 \cline{2-17}
 
@@ -308,9 +308,9 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{1} &
 \multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{2}{c|}{00} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{01} & C.SUBW {\em \tiny (RV64/128; RV32 RES)} \\
 \cline{2-17}
 
@@ -318,9 +318,9 @@
 \multicolumn{3}{|c|}{100} &
 \multicolumn{1}{c|}{1} &
 \multicolumn{2}{c|}{11} &
-\multicolumn{3}{c|}{rs1$'$/rd$'$} &
+\multicolumn{3}{c|}{\rsoneprime/\rdprime} &
 \multicolumn{2}{c|}{01} &
-\multicolumn{3}{c|}{rs2$'$} &
+\multicolumn{3}{c|}{\rstwoprime} &
 \multicolumn{2}{c|}{01} & C.ADDW {\em \tiny (RV64/128; RV32 RES)} \\
 \cline{2-17}
 
@@ -353,7 +353,7 @@
 &
 \multicolumn{3}{|c|}{110} &
 \multicolumn{3}{c|}{imm[8$\vert$4:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{5}{c|}{imm[7:6$\vert$2:1$\vert$5]} &
 \multicolumn{2}{c|}{01} & C.BEQZ \\
 \whline{2-17}
@@ -361,7 +361,7 @@
 &
 \multicolumn{3}{|c|}{111} &
 \multicolumn{3}{c|}{imm[8$\vert$4:3]} &
-\multicolumn{3}{c|}{rs1$'$} &
+\multicolumn{3}{c|}{\rsoneprime} &
 \multicolumn{5}{c|}{imm[7:6$\vert$2:1$\vert$5]} &
 \multicolumn{2}{c|}{01} & C.BNEZ \\
 \cline{2-17}