diff options
author | ds2horner <ds2horner@gmail.com> | 2017-07-01 20:42:25 -0400 |
---|---|---|
committer | Andrew Waterman <andrew@sifive.com> | 2017-07-01 22:08:54 -0700 |
commit | 6c372b544b4bed13455d711bc0ca1316ff7a7fa4 (patch) | |
tree | 50c9bb4f941aeafad6901f4da9b99324c14579f3 /src | |
parent | 2634695db445868f429978fd2b2cbaace69aeec3 (diff) | |
download | riscv-isa-manual-6c372b544b4bed13455d711bc0ca1316ff7a7fa4.zip riscv-isa-manual-6c372b544b4bed13455d711bc0ca1316ff7a7fa4.tar.gz riscv-isa-manual-6c372b544b4bed13455d711bc0ca1316ff7a7fa4.tar.bz2 |
Clarify Float Compare description
Modeled after SLT description:
Make register compare order explicit (rs1 to rs2)
Make Boolean result explicit (1 written if true, zero otherwise).
Diffstat (limited to 'src')
-rw-r--r-- | src/f.tex | 8 | ||||
-rw-r--r-- | src/q.tex | 6 |
2 files changed, 8 insertions, 6 deletions
@@ -666,9 +666,11 @@ for common mixed-format code sequences. \section{Single-Precision Floating-Point Compare Instructions} -Floating-point compare instructions perform the specified comparison (equal, -less than, or less than or equal) between floating-point registers {\em rs1} -and {\em rs2} and record the Boolean result in integer register {\em rd}. +Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the +specified comparison between floating-point registers ($\mbox{\em rs1} += \mbox{\em rs2}$, $\mbox{\em rs1} < \mbox{\em rs2}$, $\mbox{\em rs1} \leq +\mbox{\em rs2}$) writing 1 to the integer register {\em rd} if the condition +holds, and 0 otherwise. FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as {\em signaling} comparisons: that is, an Invalid Operation exception is raised if @@ -242,9 +242,9 @@ RV128 supports FMV.X.Q and FMV.Q.X in the Q extension. \section{Quad-Precision Floating-Point Compare Instructions} -Floating-point compare instructions perform the specified comparison (equal, -less than, or less than or equal) between floating-point registers {\em rs1} -and {\em rs2} and record the Boolean result in integer register {\em rd}. +The quad-precision floating-point compare instructions are +defined analogously to their double-precision counterparts, but operate on +quad-precision operands. \vspace{-0.2in} \begin{center} |