C -> 2.0

2 files changed, 3 insertions, 8 deletions

diff --git a/src/c.tex b/src/c.tex
index 3d6f689..3d2f554 100644
--- a/src/c.tex
+++ b/src/c.tex
@@ -1,5 +1,5 @@
 \chapter{``C'' Standard Extension for Compressed Instructions, Version
-1.9}
+2.0}
 \label{compressed}
 
 This chapter describes the current draft proposal for the RISC-V
@@ -11,12 +11,6 @@ generic term ``RVC'' to cover any of these.  Typically, 50\%--60\% of
 the RISC-V instructions in a program can be replaced with RVC
 instructions, resulting in a 25\%--30\% code-size reduction.
 
-We believe this draft represents the close to final design for RV32C
-and RV64C (it seems premature to freeze R128C), though we are
-requesting one more round of comments, hence the 1.9 revision number.
-Please send your comments to the {\tt isa-dev} mailing list at {\tt
-  isa-dev@lists.riscv.org}.
-
 \section{Overview}
 
 RVC uses a simple compression scheme that offers shorter 16-bit
diff --git a/src/preface.tex b/src/preface.tex
index 755745b..104e7c1 100644
--- a/src/preface.tex
+++ b/src/preface.tex
@@ -22,7 +22,7 @@ versions of the RISC-V ISA modules:
     D        & 2.0 & Y \\
     Q        & 2.0 & Y \\
     L        & 0.0 & N \\
-    C        & 1.9 & N \\
+    C        & 2.0 & Y \\
     B        & 0.0 & N \\
     J        & 0.0 & N \\
     T        & 0.0 & N \\
@@ -70,6 +70,7 @@ The major changes in this version of the document include:
 \item An expanded pseudoinstruction listing.
 \item Removal of the calling convention chapter, which has been superseded by
       the RISC-V ELF psABI Specification~\cite{riscv-elf-psabi}.
+\item The C extension has been frozen and renumbered version 2.0.
 \end{itemize}
 
 \section*{Preface to Document Version 2.1}