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| author | Andrew Waterman <andrew@sifive.com> | 2024-03-18 15:08:34 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-03-18 15:08:34 -0700 |
| commit | 586e9e4bfa7f2d2a1ea3aecaded4c19147cf246b (patch) | |
| tree | 784f2df465b80db953a674ca8be26df1a746f432 /src | |
| parent | 7d4b5c875c5aaa318025148ec9cf06419b8d000e (diff) | |
| download | riscv-isa-manual-586e9e4bfa7f2d2a1ea3aecaded4c19147cf246b.zip riscv-isa-manual-586e9e4bfa7f2d2a1ea3aecaded4c19147cf246b.tar.gz riscv-isa-manual-586e9e4bfa7f2d2a1ea3aecaded4c19147cf246b.tar.bz2 | |
Clarify that vsetvli x0,x0 is reserved when vill was 1 beforehand
See discussion at https://lists.riscv.org/g/tech-vector-ext/message/846
Diffstat (limited to 'src')
| -rw-r--r-- | src/v-st-ext.adoc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc index 98344fe..4821be9 100644 --- a/src/v-st-ext.adoc +++ b/src/v-st-ext.adoc @@ -1240,8 +1240,9 @@ vector length in `vl` is used as the AVL, and the resulting value is written to `vl`, but not to a destination register. This form can only be used when VLMAX and hence `vl` is not actually changed by the new SEW/LMUL ratio. Use of the instruction with a new SEW/LMUL ratio -that would result in a change of VLMAX is reserved. Implementations -may set `vill` in this case. +that would result in a change of VLMAX is reserved. +Use of the instruction is also reserved if `vill` was 1 beforehand. +Implementations may set `vill` in either case. NOTE: This last form of the instructions allows the `vtype` register to be changed while maintaining the current `vl`, provided VLMAX is not |