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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-01 12:34:34 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-02-01 13:14:17 -0800 |
| commit | 45e064d85a0a37f4e8296f09a50495b8d83f9409 (patch) | |
| tree | f297f50c83ae91da4e2b09e05d2ef4ba046355ed /src | |
| parent | b78e422b365d26c448badcf7a7a76d5c3ae93cd3 (diff) | |
| download | riscv-isa-manual-45e064d85a0a37f4e8296f09a50495b8d83f9409.zip riscv-isa-manual-45e064d85a0a37f4e8296f09a50495b8d83f9409.tar.gz riscv-isa-manual-45e064d85a0a37f4e8296f09a50495b8d83f9409.tar.bz2 | |
Make the mcause table easier to find.
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index 2638250..c767cd2 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1044,7 +1044,7 @@ address in the BASE field. When MODE=Vectored, all synchronous exceptions into machine mode cause the {\tt pc} to be set to the address in the BASE field, whereas interrupts cause the {\tt pc} to be set to the address in the BASE field plus four times the interrupt cause number. For example, -a machine-mode timer interrupt (see Table~\ref{mcauses}) causes the {\tt pc} +a machine-mode timer interrupt (see Table~\ref{mcauses} on page~\pageref{mcauses}) causes the {\tt pc} to be set to BASE+{\tt 0x1c}. \begin{commentary} @@ -1155,7 +1155,7 @@ MXLEN \\ \end{figure} {\tt medeleg} has a bit position allocated for every synchronous exception -shown in Table~\ref{mcauses}, with the index of the bit position equal to the +shown in Table~\ref{mcauses} on page~\pageref{mcauses}, with the index of the bit position equal to the value returned in the {\tt mcause} register (i.e., setting bit 8 allows user-mode environment calls to be delegated to a lower-privilege trap handler). |