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author | Andrew Waterman <andrew@sifive.com> | 2018-12-20 13:26:07 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2018-12-20 13:26:07 -0800 |
commit | 244fbcc4eb061862f3e74d80e9e5cc2baecd86dd (patch) | |
tree | 9e7f86f546cc3ed2fac3639aed1b391f6db4e84e /src | |
parent | a1bcac1c46ea59cd45380d4e97bcbdb1a84eb44c (diff) | |
download | riscv-isa-manual-244fbcc4eb061862f3e74d80e9e5cc2baecd86dd.zip riscv-isa-manual-244fbcc4eb061862f3e74d80e9e5cc2baecd86dd.tar.gz riscv-isa-manual-244fbcc4eb061862f3e74d80e9e5cc2baecd86dd.tar.bz2 |
Improve description of IEEE exception-flag setting
This makes the distinction between RISC-V exceptions and IEEE exceptions clearer.
Diffstat (limited to 'src')
-rw-r--r-- | src/f.tex | 19 |
1 files changed, 9 insertions, 10 deletions
@@ -227,10 +227,8 @@ rounding modes. The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the -field was last reset by software, as shown in Table~\ref{bitdef}. In -floating-point instruction descriptions, the phrase ``raise an -exception'' when applied to an IEEE floating-point exception means to -set an exception flag in the {\tt fflags} CSR. The base RISC-V ISA +field was last reset by software, as shown in Table~\ref{bitdef}. +The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag. @@ -418,7 +416,7 @@ FMAX.S write, respectively, the smaller or larger of {\em rs1} and {\em rs2} to {\em rd}. For the purposes of these instructions only, the value $-0.0$ is considered to be less than the value $+0.0$. If both inputs are NaNs, the result is the canonical NaN. If only one operand is a NaN, the result is the -non-NaN operand. Signaling NaN inputs raise the invalid operation exception, +non-NaN operand. Signaling NaN inputs set the invalid operation exception flag, even when the result is not NaN. \begin{commentary} @@ -511,7 +509,7 @@ src3 & S & src2 & src1 & RM & dest & F[N]MADD/F[N]MSUB \\ non-orthogonal. \end{commentary} -The fused multiply-add instructions must raise the invalid operation exception +The fused multiply-add instructions must set the invalid operation exception flag when the multiplicands are $\infty$ and zero, even when the addend is a quiet NaN. \begin{commentary} @@ -564,7 +562,7 @@ Output for $+\infty$ or NaN & $2^{31}-1$ & $2^{32}-1$ & $2^{63}-1$ & $2^{64}-1$ All floating-point to integer and integer to floating-point conversion instructions round according to the {\em rm} field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W {\em rd}, -{\tt x0}, which will never raise any exceptions. +{\tt x0}, which will never set any exception flags. \vspace{-0.2in} \begin{center} @@ -715,9 +713,10 @@ specified comparison between floating-point registers ($\mbox{\em rs1} holds, and 0 otherwise. FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as {\em -signaling} comparisons: that is, an Invalid Operation exception is raised if -either input is NaN. FEQ.S performs a {\em quiet} comparison: only signaling -NaN inputs cause an Invalid Operation exception. For all three instructions, +signaling} comparisons: that is, they set the invalid operation exception flag +if either input is NaN. FEQ.S performs a {\em quiet} comparison: it only +sets the invalid operation exception flag if either input is a signaling NaN. +For all three instructions, the result is 0 if either operand is NaN. \vspace{-0.2in} |