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| author | Andrew Waterman <andrew@sifive.com> | 2024-07-02 20:02:58 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-02 20:02:58 -0700 |
| commit | 077e6277dc26412665f8e7f3b1bb4e8615cb4e21 (patch) | |
| tree | fe08b5fe5df801be9153636064e1bd9c932d6b88 /src | |
| parent | 35eb3948bf0b87c83fab5a7238bd68b6211faf62 (diff) | |
| parent | 257e5ca096725b1fabc73f674a9a780d76e3e7fc (diff) | |
| download | riscv-isa-manual-077e6277dc26412665f8e7f3b1bb4e8615cb4e21.zip riscv-isa-manual-077e6277dc26412665f8e7f3b1bb4e8615cb4e21.tar.gz riscv-isa-manual-077e6277dc26412665f8e7f3b1bb4e8615cb4e21.tar.bz2 | |
Merge pull request #1495 from riscv/htimedelta-mandatoryriscv-isa-release-35eb394-2024-07-03riscv-isa-release-077e627-2024-07-03
Clarify htimedelta is mandatory if time exists
Diffstat (limited to 'src')
| -rw-r--r-- | src/hypervisor.adoc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index d8a77e0..e63c32b 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -726,6 +726,9 @@ When XLEN=32, `htimedeltah` is a 32-bit read/write register that aliases bits 63:32 of `htimedelta`. Register `htimedeltah` does not exist when XLEN=64. +If the `time` CSR is implemented, `htimedelta` (and `htimedeltah` for XLEN=32) +must be implemented. + ==== Hypervisor Trap Value (`htval`) Register The `htval` register is an HSXLEN-bit read/write register formatted as |