Pulling in the Zc chapter.

Pulling in the Zc chapter.

1 files changed, 49 insertions, 0 deletions

diff --git a/src/zc/c_sext_h.adoc b/src/zc/c_sext_h.adoc
new file mode 100644
index 0000000..82a64db
--- /dev/null
+++ b/src/zc/c_sext_h.adoc
@@ -0,0 +1,49 @@
+<<<
+[#insns-c_sext_h,reftext="Sign extend halfword, 16-bit encoding"]
+=== c.sext.h
+
+Synopsis::
+Sign extend halfword, 16-bit encoding
+
+Mnemonic::
+c.sext.h _rd'/rs1'_
+
+Encoding (RV32, RV64)::
+[wavedrom, , svg]
+....
+{reg:[
+    { bits:  2, name: 0x1, attr: ['C1'] },
+    { bits:  3, name: 0x3, attr: ['C.SEXT.H'] },
+    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
+    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
+    { bits:  3, name: 0x7 },
+    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
+],config:{bits:16}}
+....
+
+Description::
+This instruction takes a single source/destination operand. 
+It sign-extends the least-significant halfword in the operand to XLEN bits by copying the most-significant bit
+in the halfword (i.e., bit 15) to all of the more-significant bits.
+
+[NOTE]
+  _rd'/rs1'_ is from the standard 8-register set x8-x15.
+
+Prerequisites::
+Zbb is also required.
+
+32-bit equivalent::
+<<insns-sext_h>> from Zbb
+
+[NOTE]
+
+  The SAIL module variable for _rd'/rs1'_ is called _rsdc_.
+
+Operation::
+[source,sail]
+--
+X(rsdc) = EXTS(X(rsdc)[15..0]);
+--
+
+include::Zcb_footer.adoc[]
+