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author | Bill Traynor <wmat@riscv.org> | 2024-01-31 14:33:09 -0500 |
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committer | Bill Traynor <wmat@riscv.org> | 2024-01-31 14:33:09 -0500 |
commit | ad672f9e8f8d9aa8f3f65b8c6aeda9eba2e25f8a (patch) | |
tree | 2a2592491c7fabe08b10bf2f413d9d3d57039bf5 /src/zc/c_mul.adoc | |
parent | a209a72ac7978683f8907c23dd0138a5608ad962 (diff) | |
download | riscv-isa-manual-ad672f9e8f8d9aa8f3f65b8c6aeda9eba2e25f8a.zip riscv-isa-manual-ad672f9e8f8d9aa8f3f65b8c6aeda9eba2e25f8a.tar.gz riscv-isa-manual-ad672f9e8f8d9aa8f3f65b8c6aeda9eba2e25f8a.tar.bz2 |
Pulling in the Zc chapter.
Pulling in the Zc chapter.
Diffstat (limited to 'src/zc/c_mul.adoc')
-rw-r--r-- | src/zc/c_mul.adoc | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/zc/c_mul.adoc b/src/zc/c_mul.adoc new file mode 100644 index 0000000..d2f5a21 --- /dev/null +++ b/src/zc/c_mul.adoc @@ -0,0 +1,48 @@ +<<< +[#insns-c_mul,reftext="Multiply, 16-bit encoding"] +=== c.mul + +Synopsis:: +Multiply, 16-bit encoding + +Mnemonic:: +c.mul _rsd'_, _rs2'_ + +Encoding (RV32, RV64):: +[wavedrom, , svg] +.... +{reg:[ + { bits: 2, name: 0x1, attr: ['C1'] }, + { bits: 3, name: 'rs2\'', attr: ['SRC2'] }, + { bits: 2, name: 0x2, attr: ['FUNCT2'] }, + { bits: 3, name: 'rd\'/rs1\'', attr: ['SRCDST'] }, + { bits: 3, name: 0x7 }, + { bits: 3, name: 0x4, attr: ['FUNCT3'] }, +],config:{bits:16}} +.... + +Description:: +This instruction multiplies XLEN bits of the source operands from _rsd'_ and _rs2'_ and writes the lowest XLEN bits of the result to _rsd'_. + +[NOTE] + _rd'/rs1'_ and _rs2'_ are from the standard 8-register set x8-x15. + +Prerequisites:: +M or Zmmul must be configured. + +32-bit equivalent:: +<<insns-mul>> + +[NOTE] + + The SAIL module variable for _rd'/rs1'_ is called _rsdc_, and for _rs2'_ is called _rs2c_. + +Operation:: +[source,sail] +-- +let result_wide = to_bits(2 * sizeof(xlen), signed(X(rsdc)) * signed(X(rs2c))); +X(rsdc) = result_wide[(sizeof(xlen) - 1) .. 0]; +-- + +include::Zcb_footer.adoc[] + |