diff options
| -rw-r--r-- | src/intro.tex | 19 | ||||
| -rw-r--r-- | src/machine.tex | 2 | ||||
| -rw-r--r-- | src/preamble.tex | 1 | ||||
| -rw-r--r-- | src/rv32.tex | 2 | ||||
| -rw-r--r-- | src/supervisor.tex | 4 |
5 files changed, 25 insertions, 3 deletions
diff --git a/src/intro.tex b/src/intro.tex index 242ee8c..36d429a 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -744,3 +744,22 @@ defined solely to cause requested traps are documented here. Invisible traps are, by their nature, out of scope for this document. Instruction encodings that are not defined here and not defined by some other means may cause a fatal trap. + +\section{UNSPECIFIED Behaviors and Values} + +The architecture fully describes what implementations must do and any +constraints on what they may do. In cases where the architecture +intentionally does not constrain implementations, the term \unspecified\ +is explicitly used. + +The term \unspecified\ refers to a behavior or value that is +intentionally unconstrained. The definition of these behaviors or +values is open to extensions, platform standards, or implementations. +Extensions, platform standards, or implementation documentation may +provide normative content to further constrain cases that the base +architecture defines as \unspecified. + +Like the base architecture, extensions should fully describe allowable +behavior and values and use the term \unspecified\ for cases that are +intentionally unconstrained. These cases may be constrained or defined +by other extensions, platform standards, or implementations. diff --git a/src/machine.tex b/src/machine.tex index 176f931..d66657e 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2519,7 +2519,7 @@ extensions and widest MXLEN, as described in Section~\ref{sec:misa}. The {\tt pc} is set to an implementation-defined reset vector. The {\tt mcause} register is set to a value indicating the cause of the reset. Writable PMP registers' A and L fields are set to 0. All -other hart state is unspecified. +other hart state is \unspecified. The {\tt mcause} values after reset have implementation-specific interpretation, but the value 0 should be returned on implementations diff --git a/src/preamble.tex b/src/preamble.tex index ed13e4e..5feba5a 100644 --- a/src/preamble.tex +++ b/src/preamble.tex @@ -138,3 +138,4 @@ \newcommand{\wlrl}{\textbf{WLRL}} \newcommand{\warl}{\textbf{WARL}} +\newcommand{\unspecified}{\textsc{unspecified}} diff --git a/src/rv32.tex b/src/rv32.tex index 78742cb..7229685 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -162,6 +162,8 @@ and to simplify hardware design for systems with IALIGN=32, where these are the only places where misalignment can occur. \end{commentary} +The behavior upon decoding a reserved instruction is \unspecified. + \vspace{-0.2in} \begin{figure}[h] \begin{center} diff --git a/src/supervisor.tex b/src/supervisor.tex index 91c36d0..e2c8781 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -896,9 +896,9 @@ Value & Name & Description \\ \label{tab:satp-mode} \end{table} -The number of supervisor physical address bits is implementation-defined; any +The number of supervisor physical address bits is \unspecified; any unimplemented address bits are hardwired to zero in the {\tt satp} register. -The number of ASID bits is also implementation-defined and may be zero. The +The number of ASID bits is also \unspecified\ and may be zero. The number of implemented ASID bits, termed {\mbox {\em ASIDLEN}}, may be determined by writing one to every bit position in the ASID field, then reading back the value in {\tt satp} to see which bit positions in the ASID |