From 01069ac96b90bdc330fc4471945639a54e3b3b69 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 10 Sep 2021 04:12:41 -0700 Subject: Generalize SSIP to support forthcoming interrupt controllers (#726) * Changes to SSIP to support forthcoming interrupt controllers * Re: SSIP, say more by saying less --- src/supervisor.tex | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'src/supervisor.tex') diff --git a/src/supervisor.tex b/src/supervisor.tex index 966b483..83866df 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -475,11 +475,8 @@ the execution environment. Bits {\tt sip}.SSIP and {\tt sie}.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. -If implemented, SSIP is writable in {\tt sip}. -A supervisor-level software interrupt is triggered -on the current hart by writing 1 to SSIP, -while a pending supervisor-level software -interrupt can be cleared by writing 0 to SSIP. +If implemented, SSIP is writable in {\tt sip} and may also be set +to 1 by a platform-specific interrupt controller. \begin{commentary} Interprocessor interrupts are sent to other harts by implementation-specific -- cgit v1.1