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| author | Andrew Waterman <andrew@sifive.com> | 2023-09-16 19:50:44 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-16 19:50:44 -0700 |
| commit | 8176af1a46bfe2e15f8cdb170d74e52e1ba6efa2 (patch) | |
| tree | 3f2c5c9021e9dea4f9baad6fd47266ff01bc8b71 /src/supervisor.adoc | |
| parent | d118532afc4c28e0a377e132a1dcb0157ccf601d (diff) | |
| download | riscv-isa-manual-8176af1a46bfe2e15f8cdb170d74e52e1ba6efa2.zip riscv-isa-manual-8176af1a46bfe2e15f8cdb170d74e52e1ba6efa2.tar.gz riscv-isa-manual-8176af1a46bfe2e15f8cdb170d74e52e1ba6efa2.tar.bz2 | |
Standardize on no hyphen in illegal instruction exception (#1131)
Diffstat (limited to 'src/supervisor.adoc')
| -rw-r--r-- | src/supervisor.adoc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/supervisor.adoc b/src/supervisor.adoc index f3771ef..8e66a26 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -538,14 +538,14 @@ address of the portion of the instruction that caused the fault, while The `stval` register can optionally also be used to return the faulting instruction bits on an illegal instruction exception (`sepc` points to the faulting instruction in memory). If `stval` is written with a -nonzero value when an illegal-instruction exception occurs, then `stval` +nonzero value when an illegal instruction exception occurs, then `stval` will contain the shortest of: * the actual faulting instruction * the first ILEN bits of the faulting instruction * the first SXLEN bits of the faulting instruction -The value loaded into `stval` on an illegal-instruction exception is +The value loaded into `stval` on an illegal instruction exception is right-justified and all unused upper bits are cleared to zero. For other traps, `stval` is set to zero, but a future standard may |