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| author | Andrew Waterman <andrew@sifive.com> | 2024-06-25 20:00:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2024-06-25 20:00:13 -0700 |
| commit | d68656d445368e65afb99b7d718d6f8dd9dea539 (patch) | |
| tree | 19454b474380b288a331619bb9d9560dc2df1a2c /src/sstc.adoc | |
| parent | fbbdac0534a2434b75fe5b8886fc7beec02b0a10 (diff) | |
| download | riscv-isa-manual-d68656d445368e65afb99b7d718d6f8dd9dea539.zip riscv-isa-manual-d68656d445368e65afb99b7d718d6f8dd9dea539.tar.gz riscv-isa-manual-d68656d445368e65afb99b7d718d6f8dd9dea539.tar.bz2 | |
Clarify that timer/cofi interrupts may arrive delayed in xip
Diffstat (limited to 'src/sstc.adoc')
| -rw-r--r-- | src/sstc.adoc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/sstc.adoc b/src/sstc.adoc index 399d556..49be41a 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -41,8 +41,8 @@ Supervisor Trap Setup block of CSRs). A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the `mip` and `sip` registers whenever `time` contains a value greater than or equal to `stimecmp`, treating the values as unsigned integers. -Writes to `stimecmp` are guaranteed to be reflected in STIP eventually, but -not necessarily immediately. +If the result of this comparison changes, it is guaranteed to be reflected in +STIP eventually, but not necessarily immediately. The interrupt remains posted until `stimecmp` becomes greater than `time`, typically as a result of writing `stimecmp`. The interrupt will be taken based on the standard interrupt enable and @@ -128,8 +128,8 @@ A virtual supervisor timer interrupt becomes pending, as reflected in the VSTIP bit in the `hip` register, whenever (`time` + `htimedelta`), truncated to 64 bits, contains a value greater than or equal to `vstimecmp`, treating the values as unsigned integers. -Writes to `vstimecmp` and `htimedelta` are guaranteed to be reflected in VSTIP -eventually, but not necessarily immediately. +If the result of this comparison changes, it is guaranteed to be reflected in +VSTIP eventually, but not necessarily immediately. The interrupt remains posted until `vstimecmp` becomes greater than (`time` + `htimedelta`), typically as a result of writing `vstimecmp`. The interrupt will be taken based on the standard interrupt enable and |