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author | Bill Traynor <wmat@riscv.org> | 2023-03-29 14:44:08 -0400 |
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committer | Bill Traynor <wmat@riscv.org> | 2023-03-29 14:44:08 -0400 |
commit | 03276a4b4c695579de50bed33d063945831bd788 (patch) | |
tree | 29af83ff40433baeda6a0aa925f3ae57bf75dc4f /src/rnmi.adoc | |
parent | f8ffdbdc1d80d2606bf5a09d778f77e2d157a322 (diff) | |
download | riscv-isa-manual-03276a4b4c695579de50bed33d063945831bd788.zip riscv-isa-manual-03276a4b4c695579de50bed33d063945831bd788.tar.gz riscv-isa-manual-03276a4b4c695579de50bed33d063945831bd788.tar.bz2 |
Fixed include of mnepc.edn
Fixed include of mnepc.edn in rnmi.adoc file.
Diffstat (limited to 'src/rnmi.adoc')
-rw-r--r-- | src/rnmi.adoc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rnmi.adoc b/src/rnmi.adoc index 16672f4..e70e23f 100644 --- a/src/rnmi.adoc +++ b/src/rnmi.adoc @@ -46,7 +46,7 @@ the NMI trap handler to save and restore the context that was interrupted. .Resumable NMI program counter `mnepc`. -include::images/bytefield/mnepc.adoc[] +include::images/bytefield/mnepc.edn[] The `mnepc` CSR is an MXLEN-bit read-write register which on entry to the NMI trap handler holds the PC of the instruction that took the |