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author | ds2horner <ds2horner@gmail.com> | 2017-07-01 20:42:25 -0400 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-07-01 22:08:54 -0700 |
commit | 6c372b544b4bed13455d711bc0ca1316ff7a7fa4 (patch) | |
tree | 50c9bb4f941aeafad6901f4da9b99324c14579f3 /src/q.tex | |
parent | 2634695db445868f429978fd2b2cbaace69aeec3 (diff) | |
download | riscv-isa-manual-6c372b544b4bed13455d711bc0ca1316ff7a7fa4.zip riscv-isa-manual-6c372b544b4bed13455d711bc0ca1316ff7a7fa4.tar.gz riscv-isa-manual-6c372b544b4bed13455d711bc0ca1316ff7a7fa4.tar.bz2 |
Clarify Float Compare description
Modeled after SLT description:
Make register compare order explicit (rs1 to rs2)
Make Boolean result explicit (1 written if true, zero otherwise).
Diffstat (limited to 'src/q.tex')
-rw-r--r-- | src/q.tex | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -242,9 +242,9 @@ RV128 supports FMV.X.Q and FMV.Q.X in the Q extension. \section{Quad-Precision Floating-Point Compare Instructions} -Floating-point compare instructions perform the specified comparison (equal, -less than, or less than or equal) between floating-point registers {\em rs1} -and {\em rs2} and record the Boolean result in integer register {\em rd}. +The quad-precision floating-point compare instructions are +defined analogously to their double-precision counterparts, but operate on +quad-precision operands. \vspace{-0.2in} \begin{center} |