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author | Bill Traynor <wmat@riscv.org> | 2023-04-19 11:52:11 -0400 |
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committer | Bill Traynor <wmat@riscv.org> | 2023-04-19 11:52:11 -0400 |
commit | ddae740016e10f96cdc948096c50e11150b545ba (patch) | |
tree | 051d89a591b88b8f295bb4738f70aca7db184a52 /src/priv-csrs.adoc | |
parent | 0b721e72c36ab97444ec3b3f48dd6eecb43f2ab9 (diff) | |
download | riscv-isa-manual-ddae740016e10f96cdc948096c50e11150b545ba.zip riscv-isa-manual-ddae740016e10f96cdc948096c50e11150b545ba.tar.gz riscv-isa-manual-ddae740016e10f96cdc948096c50e11150b545ba.tar.bz2 |
Table formatting
Formatted table to match LaTeX.
Diffstat (limited to 'src/priv-csrs.adoc')
-rw-r--r-- | src/priv-csrs.adoc | 148 |
1 files changed, 97 insertions, 51 deletions
diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc index adbb3d3..e84cc05 100644 --- a/src/priv-csrs.adoc +++ b/src/priv-csrs.adoc @@ -226,43 +226,68 @@ handlers. |Number |Privilege |Name |Description 4+^|Hypervisor Trap Setup -|`0x600` |HRW |`hstatus` |Hypervisor status register. - -|`0x602` |HRW |`hedeleg` |Hypervisor exception delegation register. - -|`0x603` |HRW |`hideleg` |Hypervisor interrupt delegation register. - -|`0x604` |HRW |`hie` |Hypervisor interrupt-enable register. - -|`0x606` |HRW |`hcounteren` |Hypervisor counter enable. - -|`0x607` |HRW |`hgeie` |Hypervisor guest external interrupt-enable -register. +|`0x600` + +`0x602` + +`0x603` + +`0x604` + +`0x606` + +`0x607` +|HRW + +HRW + +HRW + +HRW + +HRW + +HRW +|`hstatus` + +`hedeleg` + +`hideleg` + +`hie` + +`hcounteren` + +`hgeie` +|Hypervisor status register. + +Hypervisor exception delegation register. + +Hypervisor interrupt delegation register. + +Hypervisor interrupt-enable register. + +Hypervisor counter enable. + +Hypervisor guest external interrupt-enable register. 4+^|Hypervisor Trap Handling -|`0x643` |HRW |`htval` |Hypervisor bad guest physical address. - -|`0x644` |HRW |`hip` |Hypervisor interrupt pending. - -|`0x645` |HRW |`hvip` |Hypervisor virtual interrupt pending. - -|`0x64A` |HRW |`htinst` |Hypervisor trap instruction (transformed). - -|`0xE12` |HRO |`hgeip` |Hypervisor guest external interrupt pending. +|`0x643` + +`0x644` + +`0x645` + +`0x64A` + +`0xE12` +|HRW + +HRW + +HRW + +HRW + +HRO +|`htval` + +`hip` + +`hvip` + +`htinst` + +`hgeip` +|Hypervisor bad guest physical address. + +Hypervisor interrupt pending. + +Hypervisor virtual interrupt pending. + +Hypervisor trap instruction (transformed). + +Hypervisor guest external interrupt pending. 4+^|Hypervisor Configuration -|`0x60A` |HRW |`henvcfg` |Hypervisor environment configuration -register. - -|`0x61A` |HRW |`henvcfgh` |Additional hypervisor env. conf. register, -RV32 only. +|`0x60A` + +`0x61A` +|HRW + +HRM +|`henvcfg` + +`henvcfgh` +|Hypervisor environment configuration register. + +Additional hypervisor env. conf. register, RV32 only. + 4+^|Hypervisor Protection and Translation -|`0x680` |HRW |`hgatp` |Hypervisor guest address translation and -protection. +|`0x680` |HRW |`hgatp` |Hypervisor guest address translation and protection. 4+^|Debug/Trace Registers @@ -270,32 +295,53 @@ protection. 4+^|Hypervisor Counter/Timer Virtualization Registers -|`0x605` |HRW |`htimedelta` |Delta for VS/VU-mode timer. - -|`0x615` |HRW |`htimedeltah` |Upper 32 bits of `htimedelta`, HSXLEN=32 -only. +|`0x605` + +`0x615` +|HRW + +HRW +|`htimedelta` + +`htimedeltah` +|Delta for VS/VU-mode timer. + +Upper 32 bits of `htimedelta`, HSXLEN=32 only. 4+^|Virtual Supervisor Registers -|`0x200` |HRW |`vsstatus` |Virtual supervisor status register. - -|`0x204` |HRW |`vsie` |Virtual supervisor interrupt-enable register. - -|`0x205` |HRW |`vstvec` |Virtual supervisor trap handler base address. - -|`0x240` |HRW |`vsscratch` |Virtual supervisor scratch register. - -|`0x241` |HRW |`vsepc` |Virtual supervisor exception program counter. - -|`0x242` |HRW |`vscause` |Virtual supervisor trap cause. - -|`0x243` |HRW |`vstval` |Virtual supervisor bad address or -instruction. - -|`0x244` |HRW |`vsip` |Virtual supervisor interrupt pending. - -|`0x280` |HRW |`vsatp` |Virtual supervisor address translation and -protection. +|`0x200` + +`0x204` + +`0x205` + +`0x240` + +`0x241` + +`0x242` + +`0x243` + +`0x244` + +`0x280` +|HRW + +HRW + +HRW + +HRW + +HRW + +HRW + +HRW + +HRW + +HRW +|`vsstatus` + +`vsie` + +`vstvec` + +`vsscratch` + +`vsepc` + +`vscause` + +`vstval` + +`vsip` + +`vsatp` +|Virtual supervisor status register. + +Virtual supervisor interrupt-enable register. + +Virtual supervisor trap handler base address. + +Virtual supervisor scratch register. + +Virtual supervisor exception program counter. + +Virtual supervisor trap cause. + +Virtual supervisor bad address or instruction. + +Virtual supervisor interrupt pending. + +Virtual supervisor address translation and protection. |=== <<< |