Table formatting.

Table formatting to match LaTeX.
Replaced symbols with html code.

1 files changed, 143 insertions, 77 deletions

diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc
index 40f2dab..adbb3d3 100644
--- a/src/priv-csrs.adoc
+++ b/src/priv-csrs.adoc
@@ -307,92 +307,158 @@ protection.
 |Number |Privilege |Name |Description
 4+^|Machine Information Registers
 
-|`0xF11` |MRO |`mvendorid` |Vendor ID.
-
-|`0xF12` |MRO |`marchid` |Architecture ID.
-
-|`0xF13` |MRO |`mimpid` |Implementation ID.
-
-|`0xF14` |MRO |`mhartid` |Hardware thread ID.
-
-|`0xF15` |MRO |`mconfigptr` |Pointer to configuration data structure.
+|`0xF11` +
+`0xF12` +
+`0xF13` +
+`0xF14` +
+`0xF15`
+|MRO +
+MRO +
+MRO +
+MRO +
+MRO
+|`mvendorid` +
+`marchid` +
+`mimpid` +
+`mhartid` +
+`mconfigptr`
+|Vendor ID. +
+Architecture ID. +
+Implementation ID. +
+Hardware thread ID. +
+Pointer to configuration data structure.
 
 4+^|Machine Trap Setup
 
-|`0x300` |MRW |`mstatus` |Machine status register.
-
-|`0x301` |MRW |`misa` |ISA and extensions
-
-|`0x302` |MRW |`medeleg` |Machine exception delegation register.
-
-|`0x303` |MRW |`mideleg` |Machine interrupt delegation register.
-
-|`0x304` |MRW |`mie` |Machine interrupt-enable register.
-
-|`0x305` |MRW |`mtvec` |Machine trap-handler base address.
-
-|`0x306` |MRW |`mcounteren` |Machine counter enable.
-
-|`0x310` |MRW |`mstatush` |Additional machine status register, RV32
-only.
+|`0x300` +
+`0x301` +
+`0x302` +
+`0x303` +
+`0x304` +
+`0x305` +
+`0x306` +
+`0x310`
+|MRW +
+MRW +
+MRW +
+MRW +
+MRW +
+MRW +
+MRW +
+MRW  
+|`mstatus` +
+`misa` + 
+`medeleg` +
+`mideleg` +
+`mie` +
+`mtvec` +
+`mcounteren` +
+`mstatush` 
+|Machine status register. +
+ISA and extensions +
+Machine exception delegation register. +
+Machine interrupt delegation register. +
+Machine interrupt-enable register. +
+Machine trap-handler base address. +
+Machine counter enable. +
+Additional machine status register, RV32 only.
 
 4+^|Machine Trap Handling
 
-|`0x340` |MRW |`mscratch` |Scratch register for machine trap handlers.
-
-|`0x341` |MRW |`mepc` |Machine exception program counter.
-
-|`0x342` |MRW |`mcause` |Machine trap cause.
-
-|`0x343` |MRW |`mtval` |Machine bad address or instruction.
-
-|`0x344` |MRW |`mip` |Machine interrupt pending.
-
-|`0x34A` |MRW |`mtinst` |Machine trap instruction (transformed).
-
-|`0x34B` |MRW |`mtval2` |Machine bad guest physical address.
+|`0x340` +
+`0x341` +
+`0x342` +
+`0x343` +
+`0x344` +
+`0x34A` +
+`0x34B` 
+|MRW +
+MRW +
+MRW +
+MRW +
+MRW +
+MRW +
+MRW
+|`mscratch` +
+`mepc` +
+`mcause` +
+`mtval` +
+`mip` +
+`mtinst` +
+`mtval2` 
+|Scratch register for machine trap handlers. +
+Machine exception program counter. +
+Machine trap cause. +
+Machine bad address or instruction. +
+Machine interrupt pending. +
+Machine trap instruction (transformed). +
+Machine bad guest physical address.
 
 4+^|Machine Configuration
 
-|`0x30A` |MRW |`menvcfg` |Machine environment configuration register.
-
-|`0x31A` |MRW |`menvcfgh` |Additional machine env. conf. register,
-RV32 only.
-
-|`0x747` |MRW |`mseccfg` |Machine security configuration register.
-
-|`0x757` |MRW |`mseccfgh` |Additional machine security conf. register,
-RV32 only.
+|`0x30A` +
+`0x31A` +
+`0x747` +
+`0x757` 
+|MRW +
+MRW +
+MRW +
+MRW  
+|`menvcfg` +
+`menvcfgh` + 
+`mseccfg` +
+`mseccfgh`
+|Machine environment configuration register. +
+Additional machine env. conf. register, RV32 only. +
+Machine security configuration register. +
+Additional machine security conf. register, RV32 only.
 
 4+^|Machine Memory Protection
 
-|`0x3A0` |MRW |`pmpcfg0` |Physical memory protection configuration.
-
-|`0x3A1` |MRW |`pmpcfg1` |Physical memory protection configuration,
-RV32 only.
-
-|`0x3A2` |MRW |`pmpcfg2` |Physical memory protection configuration.
-
-|`0x3A3` |MRW |`pmpcfg3` |Physical memory protection configuration,
-RV32 only.
-
-| | ^|⋮ |
-
-|`0x3AE` |MRW |`pmpcfg14` |Physical memory protection configuration.
-
-|`0x3AF` |MRW |`pmpcfg15` |Physical memory protection configuration,
-RV32 only.
-
-|`0x3B0` |MRW |`pmpaddr0` |Physical memory protection address
-register.
-
-|`0x3B1` |MRW |`pmpaddr1` |Physical memory protection address
-register.
-
-| | ^|⋮ |
-
-|`0x3EF` |MRW |`pmpaddr63` |Physical memory protection address
-register.
+|`0x3A0` +
+`0x3A1` +
+`0x3A2` +
+`0x3A3` +
+  +
+`0x3AE` +
+`0x3AF` +
+`0x3B0` +
+`0x3B1` +
+  +
+`0x3EF`
+|MRW +
+MRW +
+MRW +
+MRW +
+  +
+MRW +
+MRW +
+MRW +
+MRW +
+  +
+MRW
+|`pmpcfg0` +
+`pmpcfg1` +
+`pmpcfg2` +
+`pmpcfg3` +
+⋯ +
+`pmpcfg14` + 
+`pmpcfg15` +
+`pmpaddr0` +
+`pmpaddr1` +
+⋯ +
+`pmpaddr63`
+|Physical memory protection configuration. +
+Physical memory protection configuration, RV32 only. +
+Physical memory protection configuration. +
+Physical memory protection configuration, RV32 only. +
+  +
+Physical memory protection configuration. +
+Physical memory protection configuration, RV32 only. +
+Physical memory protection address register. +
+Physical memory protection address register. +
+  +
+Physical memory protection address register.
 |===
 
 <<<
@@ -451,13 +517,13 @@ MRW +
 `minstret` +
 `mhpmcounter3` +
 `mhpmcounter4` +
-⋮ +
+&#8942; +
 `mhpmcounter31` +
 `mcycleh` +
 `minstreth` +
 `mhpmcounter3h` +
 `mhpmcounter4h` +
-⋮
+&#8942;
 `mhpmcounter31h`
 |Machine cycle counter. +
 Machine instructions-retired counter. +
@@ -487,7 +553,7 @@ MRW +
 |`mcountinhibit` +
 `mhpmevent3` +
 `mhpmevent4` +
-⋮ +
+&#8942; +
 `mhpmevent31` 
 |Machine counter-inhibit register. +
 Machine performance-monitoring event selector. +