Formatting table

Formatted table to match LaTeX.

1 files changed, 124 insertions, 64 deletions

diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc
index e598d8a..40f2dab 100644
--- a/src/priv-csrs.adoc
+++ b/src/priv-csrs.adoc
@@ -404,80 +404,140 @@ register.
 |Number |Privilege |Name |Description
 4+^|Machine Non-Maskable Interrupt Handling
 
-|`0x740` |MRW |`mnscratch` |Resumable NMI scratch register.
-
-|`0x741` |MRW |`mnepc` |Resumable NMI program counter.
-
-|`0x742` |MRW |`mncause` |Resumable NMI cause.
-
-|`0x744` |MRW |`mnstatus` |Resumable NMI status.
+|`0x740` +
+`0x741` +
+`0x742` +
+`0x744` 
+|MRW +
+MRW +
+MRW +
+MRW
+|`mnscratch` +
+`mnepc` +
+`mncause` +
+`mnstatus`
+|Resumable NMI scratch register. +
+Resumable NMI program counter. +
+Resumable NMI cause. +
+Resumable NMI status.
 
 4+^|Machine Counter/Timers
 
-|`0xB00` |MRW |`mcycle` |Machine cycle counter.
-
-|`0xB02` |MRW |`minstret` |Machine instructions-retired counter.
-
-|`0xB03` |MRW |`mhpmcounter3` |Machine performance-monitoring counter.
-
-|`0xB04` |MRW |`mhpmcounter4` |Machine performance-monitoring counter.
-
-| | ^|⋮ |
-
-|`0xB1F` |MRW |`mhpmcounter31` |Machine performance-monitoring
-counter.
-
-|`0xB80` |MRW |`mcycleh` |Upper 32 bits of `mcycle`, RV32 only.
-
-|`0xB82` |MRW |`minstreth` |Upper 32 bits of `minstret`, RV32 only.
-
-|`0xB83` |MRW |`mhpmcounter3h` |Upper 32 bits of `mhpmcounter3`, RV32
-only.
-
-|`0xB84` |MRW |`mhpmcounter4h` |Upper 32 bits of `mhpmcounter4`, RV32
-only.
-
-| | ^|⋮ |
-
-|`0xB9F` |MRW |`mhpmcounter31h` |Upper 32 bits of `mhpmcounter31`,
-RV32 only.
+|`0xB00` +
+`0xB02` +
+`0xB03` +
+`0xB04` +
+  +
+`0xB1F` +
+`0xB80` +
+`0xB82` +
+`0xB83` +
+`0xB84` +
+  +
+`0xB9F`
+|MRW +
+MRW +
+MRW +
+MRW +
+  +
+MRW +
+MRW +
+MRW +
+MRW +
+MRW +
+  +
+MRW +
+|`mcycle` +
+`minstret` +
+`mhpmcounter3` +
+`mhpmcounter4` +
+⋮ +
+`mhpmcounter31` +
+`mcycleh` +
+`minstreth` +
+`mhpmcounter3h` +
+`mhpmcounter4h` +
+⋮
+`mhpmcounter31h`
+|Machine cycle counter. +
+Machine instructions-retired counter. +
+Machine performance-monitoring counter. +
+Machine performance-monitoring counter. +
+  +
+Machine performance-monitoring counter. +
+Upper 32 bits of `mcycle`, RV32 only. +
+Upper 32 bits of `minstret`, RV32 only. +
+Upper 32 bits of `mhpmcounter3`, RV32 only. +
+Upper 32 bits of `mhpmcounter4`, RV32 only. +
+  +
+Upper 32 bits of `mhpmcounter31`, RV32 only.
 
 4+^|Machine Counter Setup
 
-|`0x320` |MRW |`mcountinhibit` |Machine counter-inhibit register.
-
-|`0x323` |MRW |`mhpmevent3` |Machine performance-monitoring event
-selector.
-
-|`0x324` |MRW |`mhpmevent4` |Machine performance-monitoring event
-selector.
-
-| | ^|⋮ |
+|`0x320` +
+`0x323` +
+`0x324` +
+  +
+`0x33F`
+|MRW + 
+MRW +
+MRW +
+  +
+MRW +
+|`mcountinhibit` +
+`mhpmevent3` +
+`mhpmevent4` +
+⋮ +
+`mhpmevent31` 
+|Machine counter-inhibit register. +
+Machine performance-monitoring event selector. +
+Machine performance-monitoring event selector. +
+  +
+Machine performance-monitoring event selector.
 
-|`0x33F` |MRW |`mhpmevent31` |Machine performance-monitoring event
-selector.
 
 4+^|Debug/Trace Registers (shared with Debug Mode)
 
-|`0x7A0` |MRW |`tselect` |Debug/Trace trigger register select.
-
-|`0x7A1` |MRW |`tdata1` |First Debug/Trace trigger data register.
-
-|`0x7A2` |MRW |`tdata2` |Second Debug/Trace trigger data register.
-
-|`0x7A3` |MRW |`tdata3` |Third Debug/Trace trigger data register.
-
-|`0x7A8` |MRW |`mcontext` |Machine-mode context register.
+|`0x7A0` +
+`0x7A1`  +
+`0x7A2`  +
+`0x7A3` +
+`0x7A8`
+|MRW +
+MRW +
+MRW +
+MRW +
+MRW
+|`tselect` +
+`tdata1` +
+`tdata2` +
+`tdata3` +
+`mcontext`
+
+|Debug/Trace trigger register select. +
+First Debug/Trace trigger data register. +
+Second Debug/Trace trigger data register. +
+Third Debug/Trace trigger data register. +
+Machine-mode context register.
 
 4+^|Debug Mode Registers
 
-|`0x7B0` |DRW |`dcsr` |Debug control and status register.
-
-|`0x7B1` |DRW |`dpc` |Debug program counter.
-
-|`0x7B2` |DRW |`dscratch0` |Debug scratch register 0.
-
-|`0x7B3` |DRW |`dscratch1` |Debug scratch register 1.
+|`0x7B0` +
+`0x7B1` +
+`0x7B2` +
+`0x7B3`
+|DRW +
+DRW +
+DRW +
+DRW +
+|`dcsr` +
+`dpc` +
+`dscratch0` +
+`dscratch1`
+|Debug control and status register. +
+Debug program counter. +
+Debug scratch register 0. +
+Debug scratch register 1.
 |===
 
 === CSR Field Specifications
@@ -547,9 +607,9 @@ written value and the architectural state of the hart.
 === CSR Field Modulation
 
 If a write to one CSR changes the set of legal values allowed for a
-field of a second CSR, then unless specified otherwise, the second CSR’s
+field of a second CSR, then unless specified otherwise, the second CSR's
 field immediately gets an `UNSPECIFIED` value from among its new legal values. This
-is true even if the field’s value before the write remains legal after
+is true even if the field's value before the write remains legal after
 the write; the value of the field may be changed in consequence of the
 write to the controlling CSR.
 
@@ -558,7 +618,7 @@ write to the controlling CSR.
 As a special case of this rule, the value written to one CSR may control
 whether a field of a second CSR is writable (with multiple legal values)
 or is read-only. When a write to the controlling CSR causes the second
-CSR’s field to change from previously read-only to now writable, that
+CSR's field to change from previously read-only to now writable, that
 field immediately gets an `UNSPECIFIED` but legal value, unless specified otherwise.
 
 ***