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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 00:59:38 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-08-06 00:59:38 -0700 |
| commit | 42f3c82d1a669004e0ccdd5eb6b8fa90d358141a (patch) | |
| tree | 1b0bb1627222548300e93277eb2623ce4204915d /src/preface.tex | |
| parent | 695d84330e22b39a0b8cdfc0c54bb0e390bbcefa (diff) | |
| download | riscv-isa-manual-42f3c82d1a669004e0ccdd5eb6b8fa90d358141a.zip riscv-isa-manual-42f3c82d1a669004e0ccdd5eb6b8fa90d358141a.tar.gz riscv-isa-manual-42f3c82d1a669004e0ccdd5eb6b8fa90d358141a.tar.bz2 | |
Cleaned up RV64 chapter to remove platform-specific mandates.
Diffstat (limited to 'src/preface.tex')
| -rw-r--r-- | src/preface.tex | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/preface.tex b/src/preface.tex index dd37bd5..ad1681d 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -61,6 +61,13 @@ The major changes in this version of the document include: environment interfaces rather then just mandating invisible handling of misaligned loads and stores in user mode. This behavior was already needed for definition of classic privileged architecture. +\item FENCE.TSO instruction extension added. +\item Removed prohibitions on using RV32E with other extensions. +\item Removed platform-specific mandates that certain encodings + produced illegal instruction exceptions in RV32E and RV64I chapters. +\item Counter/timer instructions are now not considered part of + mandatory base ISA, and so CSR instructions were moved into separate + chapter. \item Defined the signed-zero behavior of FMIN.{\em fmt} and FMAX.{\em fmt}, and changed their behavior on signaling-NaN inputs to conform to the minimumNumber and maximumNumber operations in the proposed IEEE 754-201x |