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AgeCommit message (Expand)AuthorFilesLines
2022-10-17Rewrite Zam draftAndrew Waterman1-1/+1
2022-08-29Standardize on {\tt pc}, rather than PCAndrew Waterman1-2/+2
2022-07-07Zmmul is ratified and is now version 1.0Andrew Waterman1-0/+1
2022-01-09Add Zihintntl spec (#810)Andrew Waterman1-0/+1
2022-01-07Zhinxmin is ratified, tooAndrew Waterman1-1/+1
2022-01-06Update version numbers for Zfh/ZfinxAndrew Waterman1-5/+5
2021-08-02Ratified Zihintpause is version 2.0Andrew Waterman1-1/+1
2021-08-02Fix format for ratified Zihintpause in preface table, part 2John Hauser1-1/+1
2021-08-02Fix format for ratified Zihintpause in preface tableJohn Hauser1-1/+1
2021-08-02Zihintpause is ratifiedJohn Hauser1-1/+1
2021-08-02Update status of various extensionsJohn Hauser1-0/+15
2020-10-17Add PAUSE instructionAndrew Waterman1-0/+1
2020-07-22Pmp wording fix (#545)Stef O'Rear1-1/+1
2020-03-16Add preface section for older version 20191213Andrew Waterman1-0/+55
2019-12-13A extension v2.1 has been ratifiedRatified-IMAFDQCAndrew Waterman1-1/+3
2019-07-23Fix extension ordering in naming chapter and prefaceAndrew Waterman1-3/+3
2019-07-21Move N extension into its own chapter in the priv specAndrew Waterman1-1/+1
2019-06-24Fix spellingAndrew Waterman1-2/+2
2019-06-21Changes to unprivileged spec for bi[g]-endian supportAndrew Waterman1-0/+7
2019-06-21Bump version of unprivileged spec to 20190621-draftAndrew Waterman1-0/+50
2019-06-08Updated preface to indicate this is now ratified spec.Krste Asanovic1-18/+18
2019-03-24Improve CSR ordering sectionAndrew Waterman1-2/+2
2019-03-05Version 20190305-Base-Ratification for ratification vote.Krste Asanovic1-4/+9
2018-11-27Add Hauser's definition of "memory access"Andrew Waterman1-1/+1
2018-11-06spelling20181106-Base-RatificationAndrew Waterman1-1/+1
2018-11-06Version ready for ratification process.Krste Asanovic1-16/+11
2018-11-06Updated status of counters. Not ready for ratification as there are issues o...Krste Asanovic1-1/+5
2018-11-06Allow access exceptions to be reported on misaligned atomic memory operations...Krste Asanovic1-0/+2
2018-11-06Bumped base I version number to 2.1 to reflect ratified memory model, exclusi...Krste Asanovic1-2/+6
2018-11-06Moved zifencetso back into main I chapter, as does not extend base ISA spec.Krste Asanovic1-2/+0
2018-11-06Gave CSR instruction module a name and a version, and made clear these are be...Krste Asanovic1-3/+4
2018-11-05Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-13/+13
2018-11-05Update preface for unemulatable misaligned excpetions reported as access exce...Krste Asanovic1-1/+2
2018-11-05tweaksAndrew Waterman1-11/+11
2018-11-05Fix spellingAndrew Waterman1-2/+2
2018-11-04Moved FENCE.I out of base I chapter into separate Zifencei chapter.Krste Asanovic1-32/+47
2018-11-04Made clear fence.tso is an optional extensionKrste Asanovic1-2/+2
2018-11-03Removed text regarding big or bi-endian operation. For now, only specifying ...Krste Asanovic1-0/+2
2018-08-28F/D extensions to v2.2Andrew Waterman1-2/+6
2018-08-26Updated several "user" references to "unprivileged".Krste Asanovic1-6/+7
2018-08-07Made cleanup pass over floating-point extensionsKrste Asanovic1-1/+4
2018-08-07Broke out actual perf counters into separate chapter.Krste Asanovic1-1/+1
2018-08-06Cleaned up RV64 chapter to remove platform-specific mandates.Krste Asanovic1-0/+7
2018-08-05Provide new description of misaligned load/store behavior compatible with pri...Krste Asanovic1-1/+8
2018-08-05update preface.Krste Asanovic1-1/+2
2018-07-06Changes to intro as part of rationalizing ISA into ISA-only versus platform-m...Krste Asanovic1-2/+7
2018-05-30Hyphenate "instruction set" when it's part of a noun phraseAndrew Waterman1-2/+2
2018-05-02Tweaks to prefaceAndrew Waterman1-3/+3
2018-05-02Updates to the memory consistency model specDaniel Lustig1-3/+6
2018-03-21John Hauser's alternative writable-misa.C proposalAndrew Waterman1-0/+2
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