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| author | Andrew Waterman <andrew@sifive.com> | 2021-09-01 13:45:40 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-09-01 13:45:40 -0700 |
| commit | 9f7f7083b0e6a546430f34da339f07a919f64164 (patch) | |
| tree | 173248b85de8afb29af9f582f59ddb743e9c3dae /src/machine.tex | |
| parent | 920dd97f1c605c26e3590c09f396bae9bdc51982 (diff) | |
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FIOM may optionally not exist in M/U systems
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 5280156..f4ef940 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2357,6 +2357,8 @@ if an atomic instruction that accesses a region ordered as device I/O has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered as though it accesses both device I/O and memory. +If S-mode is not supported, implementations may hardwire FIOM to zero. + \begin{table}[h!] \begin{center} \begin{tabular}{|c|l|} |