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AgeCommit message (Expand)AuthorFilesLines
2022-10-03Add draft of RNMI specAndrew Waterman1-0/+2
2022-08-29Standardize on {\tt pc}, rather than PCAndrew Waterman1-1/+1
2022-06-02Replaced nonstandard with non-standard.Krste Asanovic1-1/+1
2022-05-02Improve implemented/enabled textAndrew Waterman1-5/+4
2022-05-02Clarify what is meant by "implemented" (#842)John Hauser1-2/+33
2022-01-25misa.V means "V" vector extensionAndrew Waterman1-1/+1
2022-01-25Remove tentative purpose for reserved misa.B and misa.J bitsAndrew Waterman1-2/+2
2022-01-06Remove misleading text about MPRV for less-privileged modesAndrew Waterman1-3/+2
2021-12-06Remove unfriendly terminology.Krste Asanovic1-12/+2
2021-12-02Clarify that PBMTE is read-only zero if Svpbmt is not implementedAndrew Waterman1-0/+1
2021-11-30Permit speculative execution of HLV/HSV; reset hgatp.MODE, satp.MODEAndrew Waterman1-0/+2
2021-11-30Interrupts and exceptions are different things. (#788)Paul Donahue1-2/+2
2021-11-29Add menvcfg.PBMTE / henvcfg.PBMTEAndrew Waterman1-3/+13
2021-11-28Fix typoAndrew Waterman1-1/+1
2021-11-28Add VS fieldAndrew Waterman1-24/+47
2021-11-26Avoid use of "timebase"Andrew Waterman1-1/+1
2021-11-11Rewrite most instances of "hardwire" as "read-only" (#768)John Hauser1-48/+48
2021-11-04Further relax PMP/address-translation caching interactionsAndrew Waterman1-8/+12
2021-11-02Add the Svinval standard extensionDaniel Lustig1-4/+4
2021-11-01Various minor virtual memory clarificationsDaniel Lustig1-1/+2
2021-10-28Incorporate Steve's feedbackAndrew Waterman1-1/+1
2021-10-25No valid LR/SC reservation upon resetAndrew Waterman1-0/+2
2021-10-05Fix editing error in mtval/stval definitionAndrew Waterman1-41/+27
2021-10-04Clarify order in which PMP CSRs must be implementedAndrew Waterman1-1/+2
2021-09-21Add example to clarify mip.SEIP behaviorAndrew Waterman1-0/+8
2021-09-15RISC-V Foundation -> RISC-V InternationalAndrew Waterman1-5/+5
2021-09-15mip.MSIP and mie.MSIE may be hardwired zeros (#738)John Hauser1-0/+4
2021-09-14Fix apparent typo re hpmcounter*h (#735)Scott Johnson1-1/+1
2021-09-14State behavior of uncacheable accesses to cacheable locationsAndrew Waterman1-0/+13
2021-09-14Clarify that WARL fields contain legal values after reset (#734)Andrew Waterman1-0/+1
2021-09-11Rename STCE to STCD to reverse its polarityAndrew Waterman1-2/+2
2021-09-10Generalize SSIP to support forthcoming interrupt controllers (#726)Andrew Waterman1-18/+2
2021-09-10Speculative implicit reads, v2 (#724)Andrew Waterman1-0/+15
2021-09-08Merge pull request #727 from riscv/mseccfgAndrew Waterman1-0/+157
2021-09-08FIOM may be hardwired when satp is hardwiredAndrew Waterman1-1/+2
2021-09-02Describe purpose of FIOM mechanismAndrew Waterman1-0/+6
2021-09-02Pedantically clarify behavior of writing lo/hi parts of countersAndrew Waterman1-4/+5
2021-09-01FIOM may optionally not exist in M/U systemsAndrew Waterman1-0/+2
2021-08-30Fix constraint on existence of menvcfg[h]/FIOMAndrew Waterman1-2/+3
2021-08-29FIOM affects aq/rl, tooAndrew Waterman1-0/+6
2021-08-29Add henvcfg/senvcfg CSRsAndrew Waterman1-0/+92
2021-08-29Add mseccfg CSRAndrew Waterman1-0/+49
2021-08-29Designate some of SYSTEM opcode for custom useAndrew Waterman1-0/+40
2021-08-28Add mconfigptr CSR (#697)Andrew Waterman1-0/+46
2021-08-25Remove historical remark on MRET definitionAndrew Waterman1-9/+0
2021-08-18Tweak table of synchronous exception priorities (#716)John Hauser1-5/+6
2021-08-17Clarify priorities of synchronous exceptions (#715)John Hauser1-14/+30
2021-08-13Clarify when mstatus.FS may be hardwired zero (#707)John Hauser1-3/+5
2021-08-11Interrupt conditions are also evaluated on falling edgesAndrew Waterman1-1/+2
2021-08-11Generalize interrupt trap condition evaluation conditions (#705)Andrew Waterman1-1/+3
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