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| author | Jubilee <workingjubilee@gmail.com> | 2024-11-12 14:37:53 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-12 22:37:53 +0000 |
| commit | d438885deb9311d632cf811ebb0514c0349e9461 (patch) | |
| tree | 0555ed93a300aa93f867b4d7c9a134c98ca29836 /src/hypervisor.tex | |
| parent | ec3b886cec534577c29c1f646a90d4cdad867ff1 (diff) | |
| download | riscv-isa-manual-d438885deb9311d632cf811ebb0514c0349e9461.zip riscv-isa-manual-d438885deb9311d632cf811ebb0514c0349e9461.tar.gz riscv-isa-manual-d438885deb9311d632cf811ebb0514c0349e9461.tar.bz2 | |
Explain `sscratch` is only swapped by software (#1722)riscv-isa-release-d438885-2024-11-12
* Explain `sscratch` is only swapped by software
Someone familiar with the interrupt handlers of other ISAs may
incorrectly imagine that the current description means that RISCV cores
will automatically perform the swap of `sscratch` with a user register.
This is not the case: it is a recommendation disguised as a description.
Flesh it out a bit so it is less ambiguous.
* Tweak sscratch description
Signed-off-by: Andrew Waterman <aswaterman@gmail.com>
---------
Signed-off-by: Andrew Waterman <aswaterman@gmail.com>
Co-authored-by: Andrew Waterman <aswaterman@gmail.com>
Diffstat (limited to 'src/hypervisor.tex')
0 files changed, 0 insertions, 0 deletions