diff options
| -rw-r--r-- | src/c.tex | 6 | ||||
| -rw-r--r-- | src/intro.tex | 5 | ||||
| -rw-r--r-- | src/machine.tex | 13 |
3 files changed, 18 insertions, 6 deletions
@@ -28,9 +28,9 @@ versions of common 32-bit RISC-V instructions when: The C extension is compatible with all other standard instruction extensions. The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start -on any 16-bit boundary. With the addition of the C extension, JAL and -JALR instructions will no longer raise an instruction misaligned -exception. +on any 16-bit boundary, i.e., IALIGN=16. With the addition of the C +extension, no instructions can raise instruction-address-misaligned +exceptions. \pagebreak diff --git a/src/intro.tex b/src/intro.tex index 142e358..53cfe1a 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -268,6 +268,11 @@ providing compressed 16-bit instructions and relaxes the alignment constraints to allow all instructions (16 bit and 32 bit) to be aligned on any 16-bit boundary to improve code density. +We use the term IALIGN (measured in bits) to refer to the instruction-address +alignment constraint the implementation enforces. IALIGN is 32 bits in the +base ISA, but some ISA extensions, including the compressed ISA extension, +relax IALIGN to 16 bits. IALIGN may not take on any other value. + We use the term ILEN (measured in bits) to refer to the maximum instruction length supported by an implementation, and which is always a multiple of 16 bits. For implementations supporting only a base diff --git a/src/machine.tex b/src/machine.tex index 222a92a..b395a81 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -171,9 +171,11 @@ ISA observed at any level, and supports a much richer command interface without burdening hardware designs. \end{commentary} -When clearing the ``C'' bit in {\tt misa}, software must ensure that the -current {\tt pc} is 4-byte aligned and that all {\em x}{\tt epc} registers -contain 4-byte-aligned values. +Writing {\tt misa} may increase IALIGN, e.g., by disabling the ``C'' +extension. If an instruction that writes {\tt misa} increases IALIGN, and the +subsequent instruction's address is not IALIGN-bit aligned, the attempt to +fetch that subsequent instruction raises an instruction-address-misaligned +exception. \clearpage @@ -2005,6 +2007,11 @@ It then became more orthogonal to support a different {\em x}RET instruction per privilege level. \end{commentary} +The address held in the {\em x}\,{\tt epc} register has no effect on the +success of an {\em x}\,RET instruction. If the address held in {\em x}\,{\tt +epc} is misaligned or otherwise invalid, an exception is raised {\em after} +the {\em x}\,RET instruction retires. + \subsection{Wait for Interrupt} \label{wfi} |