diff options
-rw-r--r-- | src/c.tex | 2 | ||||
-rw-r--r-- | src/rvc-instr-table.tex | 6 |
2 files changed, 4 insertions, 4 deletions
@@ -1255,7 +1255,7 @@ least-significant bits set, corresponds to instructions wider than 16 bits, including those in the base ISAs. Several instructions are only valid for certain operands; when invalid, they are marked either {\em RES} to indicate that the opcode is reserved for future -standard extensions; {\em NSE} to indicate that the opcode is designated +standard extensions; {\em Custom} to indicate that the opcode is designated for custom extensions; or {\em HINT} to indicate that the opcode is reserved for microarchitectural hints (see Section~\ref{sec:rvc-hints}). diff --git a/src/rvc-instr-table.tex b/src/rvc-instr-table.tex index ab365df..68dab32 100644 --- a/src/rvc-instr-table.tex +++ b/src/rvc-instr-table.tex @@ -225,7 +225,7 @@ \multicolumn{2}{c|}{00} & \multicolumn{3}{c|}{\rsoneprime/\rdprime} & \multicolumn{5}{c|}{nzuimm[4:0]} & -\multicolumn{2}{c|}{01} & C.SRLI {\em \tiny (RV32 NSE, nzuimm[5]=1)} \\ +\multicolumn{2}{c|}{01} & C.SRLI {\em \tiny (RV32 Custom, nzuimm[5]=1)} \\ \cline{2-17} & @@ -243,7 +243,7 @@ \multicolumn{2}{c|}{01} & \multicolumn{3}{c|}{\rsoneprime/\rdprime} & \multicolumn{5}{c|}{nzuimm[4:0]} & -\multicolumn{2}{c|}{01} & C.SRAI {\em \tiny (RV32 NSE, nzuimm[5]=1)} \\ +\multicolumn{2}{c|}{01} & C.SRAI {\em \tiny (RV32 Custom, nzuimm[5]=1)} \\ \cline{2-17} & @@ -403,7 +403,7 @@ \multicolumn{1}{c|}{nzuimm[5]} & \multicolumn{5}{c|}{rs1/rd$\neq$0} & \multicolumn{5}{c|}{nzuimm[4:0]} & -\multicolumn{2}{c|}{10} & C.SLLI {\em \tiny (HINT, rd=0; RV32 NSE, nzuimm[5]=1)} \\ +\multicolumn{2}{c|}{10} & C.SLLI {\em \tiny (HINT, rd=0; RV32 Custom, nzuimm[5]=1)} \\ \cline{2-17} & |